Lucent Technologies Inc.

Alcatel Lucent

Ascend Communications, Inc.

Thomas Andrew Hoch

John Patrick Jones

Raymond Schmidt

Prasasth Reddy Palnati

Nabil N Bitar

Andrew A Long

Ronald Mark Parker

Brian Branscomb

Philip To

Patrick L DeAngelis

P K Chidambaran

Mahesh N Ganmukhi

Andrew T Hebb

Martin Kannampuzha Varghese

Eric L Reed

Brian W Branscomb

Patrick L Deangelis

The present invention provides switches and routers, preferably with fully-connected mesh fabrics, that transmit data through the switch fabric in variable-size data units. Variable-size data units allow switches and routers to provide throughputs close to hardware capabilities, eliminating the need for over-capacity hardware in the switch fabric and other components. Along with variably-size data units, preferred embodiments of this invention include scheduling methods that provide fair allocation of pre-determined bandwidths to different protocols, to different classes of service within protocols, and to different resources within the switch by use of certain weighted, fair scheduling methods. The switches and routers of this invention are particularly directed to multi-protocol, high-throughput communication applications, but may have wide applicability in systems generally where data packets are switched or routed.

Variable packet-size backplanes for switching and routing systems

The present invention relates to communications networks, and more particularly to packet switching and routing devices used in communication networks that provide efficient multicast services. The invention provides methods and systems for switching and routing of multicast data packets in two stages. In particular, in the first stage a received multicast data packet is in an internal multicast operation by an ingress line card across a switching fabric to a plurality of egress line cards through which multicast destinations of the packet are reachable. In a second stage each egress line card further replicates the data packet to the actual transmission links across which the multicast group are reachable. This invention also includes system performing this method. The invention reduces the service time for the multicast packets making it the same as for the unicast packets, and provides for better system throughput in comparison to traditional systems.

Methods and systems for efficient multicast across a mesh backplane

The present invention provides hierarchical structures of queues and schedulers for switches and routers with, preferably fully-connected, mesh fabrics, for efficiently and properly handling the quality or service requirements of multiple network services, such as ATM and IP, in switch or router. The switches of this invention provide, for example, fair allocation of bandwidths to different network services, to different QoS classes within network services, and to different resources within the switch by use of, preferably, weighted, fair scheduling methods. The switches and routers of this invention are particularly directed to multi-protocol, high-throughput communication application, but may have wide applicability in systems generally where data packets are switched or routed.

Unified scheduling and queueing architecture for a multiservice switch

A methodology is provided for fault detection and service restoration in a multiservice switch on a per flow basis. An ingress source transmits the same data over each of two redundant cores. An egress receiver selects on a per flow bass which core to utilize. Bi-directional flows are not necessarily grouped together. The basic approach to fault detection is to assume that the two cores are not in lock step, but that the shelves are continually monitoring link flows for control path data as well as user data. The path monitoring is accomplished using a combination of arbiter and aggregator functions found in the service shelves and core interface cards, respectively. The arbiter transmits link test cells to both cores on a per flow basis, wherein the link test cells traverse and are monitored by respective aggregators to and from each core. When an egress arbiter determines that a flow is bad, it initiates a switch to the alternative source core, from which the flow would continue.

Apparatus and method for flow path based fault detection and service restoration in a packet based switching system

The present invention is a methodology for controlled switchover of unicast and multicast data flows in packet based switching system. In some cases it is advantageous to purposefully support switchover of flows from one path to the other without causing loss of data. This is termed a 'controlled' or 'hitless' switchover. In accordance with the present invention switchover methodology, given that an ingress arbiter device is transmitting to both cores simultaneously, it is required that the flows to both switching cores be synchronized at an aggregator level and that an egress arbiter be given time to cease receiving packets from one Core then switch over to the other Core, and continue receiving packets.

Controlled switchover of unicast and multicast data flows in a packet based switching system

The present invention is a core interface mechanism that permits 1:N type port protection on the core side of the switch such that core bandwidth is not wasted by the direct connection of service cards to the switching core. In an exemplary embodiment, a core interface module supports up to two active service cards and one dedicated protection service card. To provide increased efficiency and lower cost the redundant service card does not strand user bandwidth in the switch core. In an exemplary embodiment, the core interface includes a plurality of core side input and output ports for coupling to the switching core and a plurality of card side input and output ports for coupling to the service cards. A data flow switch function couples between the core side ports and the card side ports. The data flow switch function operates to complete data flow paths between the core side ports and the card side ports. A link failure detector detects a communications failure on a communications link associated with one of the active service cards and alters the data flow switch function such that one or more of said data flow paths associated with one of the active service cards are switched to one of said protection cards. The bandwidth allotment between the service cards and the interface device is generally greater than available bandwidth between the switching core and the interface device, thereby enabling connection of the protection cards without corresponding usage of switching core bandwidth.

Apparatus and method for redundancy of processing modules interfaced to a switching core

A method is presented which allows for the testing and verification of an off-line switch fabric used in network switch having redundant switch fabrics. A special test cell is directed to the off-line switch fabric, loops through a portion of the switching core of the off-line switch fabric, and is returned from the off-line switch fabric. A plurality of test cells can be used to provide full mesh connectivity checking of the off-line switch fabric. Testing is accomplished without need for reconfiguration of the off-line switch fabric, and the off-line switch fabric is available for use immediately upon determination of the need therefor.

Switch fabric testing

A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

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Boxborough, MA, United States of America

Thomas Andrew Hoch