Everspin Technologies, Inc.

Motorola Corporation

Freescale Semiconductor,inc.

Andre, Thomas

Alam, Syed M.

Gogl, Dietmar

Thomas Andre

Syed M Alam

Chitra K Subramanian

Joseph J Nahas

Halbert S Lin

Bradley J Garni

Dietmar Gogl

Sanjeev Aggarwal

Jon Michael Slaughter

Kerry Joseph Nagel

Sarin A Deshpande

Dimitri Houssameddine

Matthew Ronald Croft

Mark A Durlam

Brad John Garni

Nicholas David Rizzo

Bradley Neal Engel

Saied N Tehrani

Sumio Ikegawa

Javed S Barkatullah

Jijun Sun

Brian R Butcher

Mark F Deherrera

Yaojun Zhang

Han Kyu Lee

Frederick Charles Neumeyer

Gregory W Grynkewich

Frederick B Mancoff

Eric John Salter

Mark DeHerrera

Jean Lasseuguette

Loren J Wise

Clarance J Tracy

William Meadows

Bradley Engel

Brian Butcher

Matthew R Croft

The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

Magnetoresistive stack/structure and methods therefor

Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Methods of forming magnetoresistive devices and integrated circuits

In-plane spin orbit torque magnetoresistive stack/structure and methods therefor

In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Memory device with shared amplifier circuitry

The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

Shared spin-orbit-torque write line in a spin-orbit-torque MRAM

Magnetoresistive device design and process integration with surrounding circuitry

A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Delayed write-back in memory

The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.

Feed forward bias system for MTJ voltage control

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Short detection and inversion

A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction is performed by the memory device on each of the ECC words associated with a page, and a second level of error correction is performed on the data output by each of the input/output pads, during a particular period of time. Each of the one or more input/output pads of the memory device is configured to provide only one bit of data per ECC word to an external source during an access from the external source.

ECC word configuration for system-level ECC compatibility

In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

Circuit for wordline autobooting in memory and method therefor

The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.

Bitline control in differential magnetic memory

In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Growing community of inventors

Austin, TX, United States of America

Thomas Andre