Stmicroelectronics S.a.

Thomas Alofs

Andrew Cofler

Nicolas Grossier

Paul Armagnat

Sébastien Ferroussat

Laurent Uguen

Marc Beaujoin

The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Method of testing a sequential access memory plane and a corresponding sequential access memory semiconductor device

A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

High priority guard transfer for execution control of dependent guarded instructions

A device generates an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type. The device includes: a first block to receive a first signal representative of an actually executed instruction; a second block to receive a second signal representative of an expanded instruction; a third block to receive a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the microcontroller, microprocessor or data processing unit; at least one register to store consecutive addresses pointed to by a program counter; a fourth block to process the first, second and third signals in order to determine a pair having a source address and a destination address for an address branch, when appropriate; and a storage unit to store said address pair.

Branch tracing generator device and method for a microprocessor supporting predicated instructions and expanded instructions

A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

Multiplexed flip-flop electronic device

A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.

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Grenoble, France

Thomas Alofs