Alliance Semiconductor Corporation

Thomas Alexander

Chitranjan N Reddy

Bharat Sastri

Andrew D Daniel

The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller. The embodiments of the present invention could be implemented with discrete components or could be implemented on a single semiconductor substrate.

High speed/low speed interface with prediction cache

A perspective texture mapping circuit (10) is disclosed. In a perspective texture mapping mode, an inverse z gradient and corresponding inverse z polygon vertex value is loaded into a first interpolator circuit (14), and texture address product gradients with corresponding polygon vertex texture address product values are loaded into a second and third interpolator circuit (16 and 18). The first interpolator circuit (14) interpolates a sequence of inverse z values for the surface of the polygon. The second and third interpolator circuits (16 and 18) interpolate corresponding texture address product values for each interpolated inverse z value. The texture address product values are divided by the corresponding inverse z value in a divider circuit (12) to generate texture address values. Texture address values are coupled to texture memory (20) to generate texel values which are passed onto an output FIFO (26). In a color interpolation mode, each pixel includes three color component. Different color component gradients and vertex color component values are coupled to each interpolator circuit (14, 16 and 18) which interpolate corresponding color component values for the surface of the polygon. Corresponding color component values are coupled together to the output FIFO (26) to generate color pixels.

Perspective texture mapping circuit having pixel color interpolation

A divider/multiplier circuit (10) is disclosed. In a divider mode, numerator terms are coupled to a normalizer (14) which generates normalized numerator values and corresponding numerator exponent values therefrom. Denominator terms are coupled to a look-up normalizer (20) which generates normalized denominator inverse values and corresponding denominator exponent values therefrom. The numerator and denominator exponent values are summed in an adder circuit (18) to generate a sum exponent value. The normalized numerator and inverse denominator values are multiplied in a multiplier circuit (16) to generate a normalized quotient value. The normalized quotient value is denormalized according to the sum exponent value. In a multiply mode of operation first and second multiplicands are coupled to the multiplier circuit (16). In a high precision divide mode, a sequence of numerator and inverse denominator values are coupled to the multiplier circuit (16) to generate a sequence of partial product terms. The partial product terms are accumulated in a high precision loop (24) to provide a high precision division value. Negative multiplicands and numerator values are handled by a leading absolute value generator (12) which generates the absolute value of the multiplicand or numerator value. A trailing signed value generator (22) additively inverts the product or quotient if the multiplicand or numerator value was negative.

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Santa Clara, CA, United States of America

Thomas Alexander