International Business Machines Corporation

Other

Motorola Corporation

Freescale Semiconductor,inc.

Thomas Alan Hoy

Terence M Potter

Michael D Snyder

Paul C Rossbach

Magnus K Bruce

Mark D Scherer

Jamshed Jalal

Christopher Hans Olson

Rajesh Bhikhubhai Patel

Belliappa Manavattira Kuttanna

Robert Thaddeus Golla

Thomas L Thomas, Jr

Michael D Carlson

David Domenic Putti

A system () uses shared resources () to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (). A reload buffer () is used in conjunction with a cache () operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal () selectively enables the pushing of data into the cache () from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

System and method for cache external writing and write shadowing

System and method for cache external writing

A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry. Further benefits is achieved by allowing multiple load misses to the same cache line to be completed from a buffer that reduces cache pipeline stalls.

Dynamically modifying queued transactions in a cache memory system

A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto. The plurality of buffers are coupled to the execution circuitry for storing the output first and second information, wherein at least one of the buffers is for storing the output first information independent of which of the first and second types of registers is specified by the first type of instruction. The second circuitry is coupled to the buffers for processing a completion stage of the first type of instruction, and writing the stored first information into at least one of the first or a second type of register in response thereto. The second circuitry also processes a completion stage of the second type of instruction, and writes the stored second information into only the third type of register in response thereto.

Method and system in an information processing system for efficient maintenance of copies of values stored within registers

A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.

Method and system for dynamically recovering a register-address-table

A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group. In response to a determination that the indication of the instruction is not stored in the particular position within the register, the exception is associated with a second priority group. In response to a determination that the indication of the instruction did not generate the exception, the exception is associated with the second priority group.

Method and system in a superscalar data processing system for the

A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.

Method and system in a data processing system for efficient management

A clamp device 10 including both fixed 10' and moveable versions 10' attached to a portion of a ladder adjustment apparatus 110 for engaging the rungs 101 of a ladder 100. The device 10 comprises a lower generally C-shaped jaw member 20 having a recess 26 to receive an adapter member 50 to grasp the rung of the ladder 100. The lower jaw member 20 is pivotally connected to a portion of the ladder adjustment apparatus 110 to accommodate the angular orientation of the adjustment apparatus 110 relative to the rungs 101 of the ladder 110.

Clamp device for a ladder adjustment apparatus

A ladder adjustment apparatus (10) which is designed to be secured to the rungs (101) of a ladder (100) whereby the apparatus (10) may be laterally shifted on the rungs (101) to position the apparatus (10) adjacent either leg (102) of the ladder without the need for physically detaching the apparatus (10) from the ladder (100).

Growing community of inventors

Austin, TX, United States of America

Thomas Alan Hoy