Infineon Technologies Ag

Thomas Aichinger

Ralf Siemieniec

Dethard Peters

Romain Esteve

Wolfgang Bergner

Daniel Kueck

Hans-Joachim Schulze

Roland Rupp

Caspar Leendertz

Rudolf Elpelt

Bernd Zippelius

Shiqin Niu

Michael Hell

Paul Ellinghaus

Florian Grasse

Thomas Basler

Ravi Keshav Joshi

Michael Stadtmueller

Gerald Unegg

Saurabh Roy

Victorina Poenariu

Gerald Rescher

Gerald Reinwald

Franz Hirler

Anton Mauder

Francisco Javier Santos Rodriguez

Carsten Von Koblinski

Hans Reisinger

Thomas Krotscheck Ostermann

Iris Moder

Frank Wolter

Stefan Krivec

Reinhard Ploss

Andre Kabakow

Christian Strenger

Karlheinz Feldrapp

Maximilian Wolfgang Feil

Andreas Hürner

Sabine Gruber

A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.

Method for annealing a gate insulation layer on a wide band gap semiconductor substrate

A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Vertical power semiconductor device including silicon carbide (sic) semiconductor body

A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

Method of producing a semiconductor device having a ferroelectric gate stack

A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.

Semiconductor device having an optical device degradation sensor

A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Method of manufacturing semiconductor device with silicon carbide body

A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.

Semiconductor device having a ferroelectric gate stack

A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

Silicon carbide field-effect transistor including shielding areas

A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

SiC device with channel regions extending along at least one of the (1-100) plane and the (-1100) plane and methods of manufacturing thereof

In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.

Transistor device with a varying gate runner resistivity per area

A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

Silicon carbide devices, semiconductor devices and methods for forming silicon carbide devices and semiconductor devices

Wide band gap semiconductor device and method for forming a wide band gap semiconductor device

An embodiment of a semiconductor device includes a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction. A body region of a first conductivity type adjoins a sidewall of the trench gate structure and includes a first body sub-region adjoining the sidewall and a second body sub-region adjoining the sidewall. At least one profile of dopants of the first conductivity type along the vertical direction includes a first doping peak in the first body sub-region and a second doping peak in the second body sub-region. A doping concentration of the first doping peak is larger than a doping concentration of the second doping peak.

Semiconductor device including trench gate structure and manufacturing method

A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Semiconductor device with silicon carbide body

A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.

SiC device and methods of manufacturing thereof

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Villach, Austria

Thomas Aichinger