International Business Machines Corporation

Thomas Adam Bartush

Richard Paul Volant

David Louis Harame

Christopher Lee Tessler

John Chester Malinowski

Dawn Tudryn Piciacchio

James J Curtin

Garth A Brooks

James R Kitcher

Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.

Modular high frequency integrated circuit structure

Polishing of a non-planar surface layer on a semiconductor substrate is conducted by providing an oxidized boron nitride polish stop layer on the semiconductor substrate, forming the non-planar surface layer on the oxidized boron nitride polish stop layer, the oxidized boron nitride polish stop layer being polish selective relative to the non-planar surface layer, and polishing the non-planar surface layer until the oxidized boron nitride polish stop layer is reached.

Polish planarizing using oxidized boron nitride as a polish stop

A process of fabricating an electrical resistor and a product produced thereby in which trimming of a resistive element of a material exhibiting thermosetting properties is accomplished by in-situ annealing of one or more regions across the width of the resistive element to certain predetermined temperatures, thereby altering the crystal properties and the sheet resistance within those regions. Annealing is preferably done by laser radiation at levels below that at which any cutting or ablation of the resistive element will occur, thus avoiding defects in the resistor or associated circuits. By controlling laser radiation and the annealing process, virtually any desired trim slope may be obtained, resulting in improved trimming accuracy. Efficiency of the process is enhanced by annealing the resistive element to obtain compound trim slopes corresponding to coarse and fine trimming of the resistive element.

Active resistor trimming by differential annealing

Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels. More particularly, the present method includes steps for: the 'lift-off' deposition of metal studs on metal wires resulting from the patterning of the layer of the first level of metallization, deposition of a first insulating layer of a material such as silicon dioxide, planarization of said first layer using a standard etch back technique with a planarization medium, until the most elevated stud is exposed, then deposition of a second insulating layer of a material such as silicon nitride over the structure and the etching of the insulator with the same mask pattern that was used to delineate the studs, in order to expose all of the remaining studs.

Method for making studs for interconnecting metallization layers at

The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF.sub.4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.

Growing community of inventors

Wappingers, NY, United States of America

Thomas Adam Bartush