International Business Machines Corporation

Thomas A Williams

Claude Louis Bertin

Francisco H De La Moneda

John Bula

Larry C Martin

William Rosenbluth

Martin D Moynihan

A CMOS circuit is disclosed which has a latent image feature for application in FET memory arrays for writable read only storage applications. A four device cross-coupled CMOS circuit is formed with minimum real estate area, so as to allow for wiring level programming into a preconditioned binary one or zero state. The preconditioned circuit will assume a preselected binary state when power is turned on. Thereafter, the circuit can be accessed for normal binary one and zero selective storage without a significant diminution in its operating characteristics, when compared with conventional CMOS cross-coupled storage circuits.

Memory cell with latent image capabilities

The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

Making LSI devices with double level polysilicon structures

A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.

MOSFET Convolved logic

Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

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Reston, VA, United States of America

Thomas A Williams