Texas Instruments Corporation

Other

Thomas A Vrotsos

Jonathan S Brodsky

Robert Steinhoff

Julian Zhiliang Chen

Ajith E Amerasekera

Zhiliang Julian Chen

Wayne T Chen

Charvaka Duvvury

E Ajith Amerasekera

Larry Baoqi Li

Yun-Shan Chang

Xin Yi Zhang

A structure is designed with an external terminal () and a reference terminal (). A first transistor () is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor () has a current path coupled between the external terminal and the substrate. A third transistor () has a current path coupled between the substrate and the reference terminal.

Bi-directional ESD protection circuit

Bi-directional electrostatic discharge (ESD) protection circuit

The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit () comprising at least one input element () is protected by a protective circuit (). The protective circuit () is operable to protect the integrated circuit () from damage due to electrostatic discharge and may be coupled to the input element (). The protective circuit () comprises a lateral NPN transistor (T) coupled to the input element () and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (). The protective circuit () also may comprise a lateral PNP transistor (T) coupled to the input element () and to the lateral NPN transistor (T). The lateral PNP transistor (T) is operable to aid in raising a potential of the base of the lateral NPN transistor (T). Alternatively, the protective circuit () also may use a PMOS transistor (P), or a PMOS transistor (P) in combination with the lateral NPN transistor (T), coupled to the input element () and to the lateral NPN transistor (T). The PMOS transistor (P) is operable to aid in raising the potential of the base of the lateral NPN transistor (T).

System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing

A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

Circuit and method for an integrated charged device model clamp

The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit ( ) comprising at least one input element ( ) is protected by a protective circuit ( ). The protective circuit ( ) is operable to protect the integrated circuit ( ) from damage due to electrostatic discharge and may be coupled to the input element ( ). The protective circuit ( ) comprises a lateral NPN transistor (T ) coupled to the input element ( ) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element ( ). The protective circuit ( ) also may comprise a lateral PNP transistor (T ) coupled to the input element ( ) and to the lateral NPN transistor (T ). The lateral PNP transistor (T ) is operable to aid in raising a potential of the base of the lateral NPN transistor (T ). Alternatively, the protective circuit ( ) also may use a PMOS traisistor (P ), or a PMOS transistor (P ) in combination with the lateral NPN transistor (T ), coupled to the input element ( ) and to the lateral NPN transistor (T ). The PMOS transistor (P ) is operable to aid in raising the potential of the base of the lateral NPN transistor (T ).

The electrostatic discharge protection circuit includes: at least two bipolar transistors Q -Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node ; a bottom one Q of the at least two bipolar transistors coupled to a common node ; at least two resistors R -Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R of the at least two resistors coupled between a base of the bottom one Q of the at least two bipolar transistors and the common node

Cascoded NPN electrostatic discharge protection circuit

A protection circuit is designed with an external terminal ( ), a reference terminal ( ) and a substrate ( ). A semiconductor body ( ) is formed by an isolation region ( ) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal ( ) connected to a common control terminal ( ) and a respective current path connected between the external terminal and the reference terminal. A capacitor ( ) is connected between the semiconductor body and the external terminal. A resistor ( ) is connected between the semiconductor body and the reference terminal.

Body-triggered ESD protection circuit

An SCR provides for increased holding voltage by decoupling the pnp and npn parasitic bipolar transistors of the SCR. In one embodiment, a N&plus; region is placed between the n&plus; region and the p&plus; region normally associated with conventional SCR devices, to formulate a new resistance. The new resistance is manifested to allow more current to flow through the new resistance rather than through the SCR parasitic pnp bipolar transistor. Since the parasitic pnp bipolar transistor no longer turns on as strongly as it would otherwise without the low resistance path through the new resistor, the holding voltage of the SCR is raised.

Tuneable holding voltage SCR ESD protection

An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128) is approximately equal to the sum of the individual holding voltages for the SCRs (126, 128), which overall holding voltage is greater than the trigger voltage. Preferably, the SCR (68) is isolated from the P substrate (92) by a P-N junction which is provided by disposing the SCR (68) within an N-tank (98).

Stacked silicon-controlled rectifier having a low voltage trigger and

A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

PNP driven NMOS ESD protection circuit

The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically &lt;0.5 pF) and series resistance (typically &lt;0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

ESD protection circuit using zener diode and interdigitated NPN

The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz-&gt;2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor. The turn-on voltage of the Zener is selected so as to be comparable to the emitter-base breakdown voltage of the NPN structure, which is only slightly higher than the power supply voltage to ensure that the ESD protection circuit will not be triggered under normal circuit operation. A forward diode string can optionally be added in series with the Zener to increase circuit trigger voltage, particularly in instances where the power supply voltage exceeds the Zener breakdown voltage. During an ESD event, when pad voltage exceeds Zener breakdown voltage, the Zener breaks down, and current flows through an associated (polysilicon) resistor to trigger the NPN of the Bipolar SCR and thus activate the BSCR to conduct the High ESD current from the associated, protected circuit.

Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS

The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz-&gt;2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor. The turn-on voltage of the Zener is selected so as to be comparable to the emitter-base breakdown voltage of the NPN structure, which is only slightly higher than the power supply voltage to ensure that the ESD protection circuit will not be triggered under normal circuit operation. During an ESD event, when pad voltage exceeds Zener breakdown voltage, the Zener breaks down, and current flows through an associated (polysilicon) resistor to trigger the PNP of the Bipolar SCR and thus activate the BSCR to conduct the High ESD current from the associated, protected circuit. BSCR resistance and Zener diode breakdown voltage values are selected which permit scaling of ESD protection circuit holding and trigger voltages for optimum compatibility with the power supply voltage.

Growing community of inventors

Plano, TX, United States of America

Thomas A Vrotsos