Memc Electronic Materials, Inc.

Thomas A Torack

John Allen Pitney

Srikanth Kommu

Gregory M Wilson

Charles Robert Lottes

Lance G Hellwig

Michael John Ries

Manabu Hamano

Andrei Stefanescu

Jiri L Vasat

Swapnil Y Dhumal

Lawrence P Flannery

A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports.

Wafer holder for supporting a semiconductor wafer during a thermal treatment process

Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

Methods for processing silicon on insulator wafers

A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100&deg; C. by exposing the front surface to a cleaning ambient comprising H , HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100&deg; C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.

Thermal annealing process for producing silicon wafers with improved surface characteristics

A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber. The system comprises a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber. The system also includes a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage. The bypass valve has an open position in which gas is permitted to flow through the bypass passage to equalize pressure between the process chamber and the wafer handling chamber and a closed position in which gas is prevented from flowing through the bypass passage to isolate the process chamber from the wafer handling chamber. In addition, the system includes a flow restrictor positioned along the bypass passage for restricting gas flow through the bypass passage to limit pressure change rates in the process chamber and the wafer handling chamber when the bypass valve is in the open position and thereby to limit a maximum velocity of gas flowing through the bypass passage.

Pressure equalization system for chemical vapor deposition reactors

A reactor for depositing an epitaxial layer on a semiconductor wafer contained within the reactor during a chemical vapor deposition process. The reactor comprises a reaction chamber sized and shaped for receiving a semiconductor wafer and an inlet passage in communication with the reaction chamber for delivering reactant gas to the reaction chamber. In addition the reactor includes a susceptor positioned in the reaction chamber for supporting the semiconductor wafer during the chemical vapor deposition process. Further, the reactor comprises an injector including a metering plate generally blocking reactant gas flow through the inlet passage. The plate has a slot extending through the plate totally within a periphery of the plate. The slot is sized for selectively restricting reactant gas flow past the plate thereby to meter reactant gas delivery to the chamber.

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Oakland, MO, United States of America

Thomas A Torack