Texas Instruments Corporation

Thomas A Schmidt

Ross Eliot Teggatz

Andrew Marshall

Joseph A Devore

Brett E Smith

Abidur Rahman

H Pooya Forghani-zadeh

Taylor R Efland

Roy Alan Hastings

Fernando D Carvajal

Jingwei Xu

Shanmuganand Chellamuthu

Stephen C Kwan

Suribhotla Rajasekhar

Kenneth G Buss

Reed Wilburn Adams

John Christian Vogt

Vikas Suma Vinay

Kee Chee Tiew

Sean Patrick McEnroe

An analog switch includes a first field effect transistor (FET) which has a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch includes a second FET which has a first terminal coupled to an output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The switch includes a switched current source which has an input coupled to a high voltage supply terminal and an output coupled to the common gate. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low voltage supply terminal.

Optimized low Ron flatness gate driver

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

Analog switch with boost current for fast turn on

Programmable power distribution switches with two-level current sensing are disclosed. In a particular example, a power distribution switch includes a programmable output device having a resistance based on a programmed maximum output current and generates an output voltage based on the resistance and a load current. The example power distribution switch also includes a reference voltage generator that is configured to generate a reference voltage corresponding to the output voltage when the load current is substantially equal to the programmed maximum output current. A current limiter is also included to reduce the load current in response to a comparison of the output voltage and the reference voltage, when the comparison is indicative of the load current exceeding the programmed maximum output current.

Programmable power distribution switches with two-level current sensing

Methods and apparatus to provide power distribution switch circuits with fast responses to hard short-circuits are disclosed. In one example, a power distribution switch to detect a hard short-circuit condition is described, comprising a switching device having a resistance between an input terminal and an output terminal, to conduct a current from an input power source having an input voltage to an output terminal having an output voltage, a voltage feedback loop having a digital output voltage to increase the resistance of the switching device in response to a short-circuit based on the output voltage, and an analog current feedback loop to increase the resistance of the switching device based on a current through the switching device and a reference current.

Power distribution switch circuits with fast responses to hard short-circuits

The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.

H-bridge circuit with shoot through current prevention during power-up

A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Current limiting circuit for high-speed low-side driver outputs

A switching regulator having a current limit with adaptive cycle skipping. A buck type switching regulator circuit is provided, including an energy storage component, such as an inductor or capacitor, and a switch for controllably providing an input current to the energy storage component. A control unit controls the on time and the off time of the switch by providing cyclically recurring control pulses to the switch that cause the switch to be on during the pulses and off otherwise. A current monitor circuit monitors a current corresponding to the input current applied to the energy storage component during the periodic control pulses. An overcurrent signal generator generates an overcurrent signal pulse upon detection of the monitored current at a level above a predetermined level corresponding to an overcurrent condition. A state machine responds to the overcurrent signal pulse and suppresses a number of the cyclically recurring control pulses, thereby controlling the period between the recurring control pulses that are not suppressed, in accordance with a predetermined algorithm that increases the number each time an overcurrent signal pulse is detected in successive periods.

Current limit with adaptive cycle skipping for switching regulators

A temperature sensing system ( ) that providing at least one detect signal related to temperature in an integrated circuit is presented. This system uses one thermal sensing circuit ( ) to detect two or more temperature thresholds (t , t ) and differentiates the temperature thresholds using time multiplexed logic control. The system ( ) capable of detecting more than two temperatures includes the thermal sensing circuit ( ) and a decode circuit ( ) with at least one detect latch ( ). Optionally, the system may include a hysteresis circuit ( ). The thermal sensing circuit ( ), connected to the integrated circuit, generates a detect signal (D ) in response to the a temperature selection signal (T ). This flexible on-board temperature monitoring solution reduces the cost of thermal feedback sensing by reducing die area and improves the correlation of detected temperatures. In addition, this solution reduces the possibility of mismatch and tracking errors between two or more sense elements.

Multiple temperature threshold sensing having a single sense element

A pulse width modulated signal generator is comprised of an N-bit ripple counter (12) that generates a down counted output value which is input to a combinatorial logic circuit for generating a pulse width that is defined as a predetermined number of clock cycles from a clock that is utilized to clock the ripple counter (12). The ripple counter (12) is cycled from a maximum value to a minimum value with the value '0000' inhibited. This count value is combined with a plurality of AND gates which also receive as an input an enable value from a input (18). When the ripple counter (12) is initiated at its maximum value, the output is pulled high and then a predetermined number of the clock pulses counted, as defined by the value of the enable word. Thereafter, the output is pulled low to define the length of the pulse.

N-bit pulse width modulated signal generator

An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.

Optimized power output clamping structure

In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

Reducing the natural current limit in a power MOS device by reducing the

A technique for which integrated circuit duty-cycle control or pulse width current limiting adaptively responds to the load, allowing a brief inrush current event upon startup of the load, while restricting long-term power dissipation to a lower value. Upon sensing an overcurrent condition, a duty cycle control circuit causes the output to be placed into a high duty-cycle mode of operation to provide sufficient power to the load. A thermal sense circuit provides additional control because if the overcurrent condition continues and the junction temperature rises to the thermal sense trip point, the duty cycle control circuit places the output in a lower duty-cycle mode.

Adaptive duty-cycle limiting for overload protection of integrated

In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

A buck-boost switch mode regulated power supply using a burst circuit topology includes a detection circuit to sense overcurrent in the high side connected power transistor. This causes the flip flop to flip which turns off the transistor. A comparator connected to the output voltage detects when the output voltage falls below the threshold value of the comparator and sends a signal to the flip flop which is reset upon the next pulse of a pulsed reset signal. When the flip flop is reset, the high side power transistor is turned back on.

Buck-boost switch mode power supply with burst topology

A bandgap reference circuit 30 includes a current generation circuit 32, a voltage generation circuit 34 connected to current generation circuit 32, and a compensation circuit connected to current generation circuit 32 and voltage generation circuit 34. Current generation circuit 32 sources a current to voltage generation circuit 34 which translates the current into a voltage. Compensation circuit 36 monitors current generation circuit 32 and provides a supplemental current to voltage generation circuit 34. Voltage generation circuit 34 receives the supplemental current and translates it into a supplemental voltage. The summation of the voltage produced by the current received by current generation circuit 32 and the supplemental voltage produced by the supplemental current received by compensation circuit 36 produces a stable reference voltage.

Growing community of inventors

Dallas, TX, United States of America

Thomas A Schmidt