Intel Corporation

Real 3-d

Thomas A Piazza

Altug Koker

Hong Jiang

Robert L Farrell

Val Gene Cook

Zeev Offen

Opher D Kahn

Michael K Dwyer

Ariel Berkovits

Prasoonkumar Surti

Peter L Doyle

Ralph Clayton Taylor

Subramaniam M Maiyuran

Michael Mantor

Aditya Sreenivas

Josh B Mastronarde

Bimal Poddar

Jorge F Garcia Pabon

Kim A Meinerth

Indraneel Ghosh

Dinakar Munagala

David W Watson

Jeffrey D Potter

Tomas G Akenine-Moller

Eric C Samson

Michael Andrew Mang

Murali Sundaresan

Steven Spangler

Shubh Shah

Brian D Rauchfuss

Bishara Shomar

Sreedevi Chalasani

Abhishek R Appu

Jin Xu

Michael Apodaca

Jon N Hasselgren

Carl Jacob Munkberg

Brian K Langendorf

Wishwesh Anil Gandhi

Saurabh Sharma

Ashutosh Garg

Daniel B Clifton

Trung Am Diep

Clifford D Hall

Douglas Raymond Moran

Steve John Clohset

Angel E Socarras

Kalyan Kumar Bhiravabhatla

William B Sadler

Scott W Cheng

Darin Starkey

Tuong P Trieu

Richard W Jensen

John A Carey

Paul A Johnson

Steven Manno

R Scott Hartog

Harri Syrja

Kevin Rogovin

Nasseh Akaaboune

David Gotwalt

Matthew Radecki

Michael Dwyer

An apparatus and method are described for a high throughput rasterizer. For example, one embodiment of an apparatus comprises: block selection logic to select a plurality of pixel blocks associated with edges of a primitive, the plurality of pixel blocks selected based on the pixel blocks having samples which are both inside and outside of the primitive; and edge determination logic to analyze samples of the plurality of pixel blocks selected by the block selection logic and responsively generate data identifying each edge of the primitive; and final mask determination logic to combine the data identifying each edge and generate a final mask representing the primitive.

Method and apparatus for a high throughput rasterizer

Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Reduced power implementation of computer instructions

A pixel input is divided into blocks. The a number of blocks is determined based on the maximum number of partial spans. Finally, the blocks are rasterized.

Rasterization based on partial spans

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Technique to share information among different cache coherency domains

A group of buffers are connected via pointers as free-lists implemented in hardware, such that shader information and output processing information can be efficiently accessed by a multi-rate shader. A free-list storage picks the first available entry. The first free entry that gets allocated then becomes a pointer to another entry.

Hardware based free lists for multi-rate shader

In embodiments described herein, graphics hardware is described to reduce the number of wasted clock cycles expended during rasterization and performs coverage test iteration in a cache coherent manner. An exemplary embodiment comprises block selection logic to select an initial block of pixels associated with edges of a primitive and edge determination logic to analyze the initial block of pixels to determine a set of fully covered quadrants of the initial block of pixels and analyze a block of pixels adjacent to the initial block of pixels to determine whether the block of adjacent pixels is void.

Hierarchical quadrant based coverage testing for rasterization

An apparatus and method for a SIMD structured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process control flow instructions and to maintain a per channel count for each channel and a control instruction count for the control flow instructions, the branch unit to enable and disable the channels based at least on the per channel count.

Method and apparatus for SIMD structured branching

A scoreboard may keep track of thread dependencies. A set of threads with a common characteristic may be grouped so that if that characteristic is changed, the group of threads can be accessed to account for that change. Examples for such a characteristic include various types of scoreboard address changes. When the characteristic is changed the group of threads are used to identify threads affected by the characteristic change.

Ordering threads as groups in a multi-threaded, multi-core graphics compute system

In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Scatter/gather capable system coherent cache

In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

Position-only shading pipeline

According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.

Recording the results of visibility tests at the input geometry object granularity

An apparatus may include a memory to store a set of triangle vertices in a triangle, a processor circuit coupled to the memory and a cache to cache a set of triangle vertex indices corresponding to triangle vertices most recently transmitted through a graphics pipeline. The apparatus may also include an autostrip vertex processing component operative on the processor circuit to receive from the memory the set of triangle vertices, compare an index for each vertex of the set of triangle vertices to determine matches to the set of cached triangle vertex indices, and shift a single vertex index into the cache, the single vertex index corresponding to a vertex miss in which a given vertex of the set of triangle vertices does not match any vertex index of the set of cached triangle vertex indices when exactly two matches to the set of cached triangle vertex indices are found.

Techniques for efficient GPU triangle list adjacency detection and handling

Growing community of inventors

Granite Bay, CA, United States of America

Thomas A Piazza