Digital Equipment Corporation

Thomas A Northrup

Robert E Stewart

Stephen R Jenkins

John V Levy

Robert Giggi

Allan E Helenius

Stanley A Lackey, Jr

A special instruction processor that connects to a central processing unit in a data processing system. The central processing unit processes a number of instructions. Instructions involving operands first retrieve the operands from memory, from general purpose registers in the central processor or the instruction stream. These operands are transferred to the special instruction processor. If the instruction is one of a predetermined set of instructions that is executed by the special instruction processor, the special instruction processor will, upon receiving the operands, generate an overriding signal that alters the operation of the central processor unit by inhibiting its processing of the operands. Instead, the special instruction processor unit, that is specifically designed to perform the operations efficiently, computes a result. When the result has been computed and the central processor has determined the location for receiving the result, the central processing unit retrieves the result and stores it. Operations are optimized if the instruction operand specifiers designate operands that are to be found in the instruction stream or the general purpose registers.

Accelerator processor for a data processing system

A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. In addition, each memory module contains a margin bit decoder that decodes various binary margin signals that are transferred to it for performing various control operations. For example, these signals can alter strobe timing in the memory module. A margin signal decoder converts the incoming binary signal into an analog strobe margin signal that may have one of several magnitudes depending upon the incoming memory module.

Memory module with means for controlling internal timing

A secondary storage facility that connects to a digital data processing system. The system includes a central processor, an associative memory and a random access memory connected to the associative memory. The secondary storage facility includes a controller and one or more direct access secondary storage units. A first bus connector interconnects the controller to a first bus from the central processor and transfers of control information are routed over this bus. The controller also connects to the associative memory so that data, together with address and control information, is routed between the random access memory and a storage unit through this second connection.

Secondary storage facility for connecting to a digital data processing

A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. It is possible for the associative memory unit to request successive transfers with one or more memory modules on an overlapped basis. Each memory module performs two successive operations during each transfer: namely, a reading operation and a successive writing operation. Control circuitry in the memory module generates a BUS OCCUPIED signal during the time interval of a reading operation that occurs during a reading memory cycle that is used to transfer data to the associative memory unit. The BUS OCCUPIED signal is transferred back to the associative memory unit to inhibit the initiation of any successive overlapped memory cycle until the completion of that reading operation.

Memory module with means for generating a control signal that inhibits a

A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle. If the address memory in the associative memory unit contains a corresponding address, the new data also is transferred to the corresponding location in the data memory. Secondary memory units, such as disk memory units, and input/output units also communicate with the back-up memory unit and the associative memory unit. For example, a disk memory unit may transfer data to locations in the back-up memory unit, and such a device transmits an address to the back-up memory unit during such transfers. If the associative memory unit contains data from a corresponding location, the contents of the addressed location are modified to indicate that the data in the corresponding back-up location has been changed.

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Westford, MA, United States of America

Thomas A Northrup