International Business Machines Corporation

Thomas A Kriz

Andrew S Potemski

Mark Elliot Andresen

Robert Kimberlin Foster

Jose Luis Ortiz

John Kwangil Chang

Timothy Albert Smith

A method, apparatus, and computer instructions for managing a set of virtual clocks in a data processing system with multiple partitions. A 'set-time-of-day' command is used in connection with each virtual clock to define a basis for its local date/time state via the following elements: (1) a partition peculiar time base reference value, and (2) a partition peculiar time offset reference value which corresponds to the state of an elapsed time counter at the point in time when the time base reference value is established. The partition time base reference and offset reference values are stored in memory. When executing a 'get-time-of-day' command, these are retrieved along with the current state of the elapsed time counter facility to compute the current date/time state of the virtual clock for the partition.

Method and apparatus for generating a virtual clock in a data processing system

A method and system for providing a timed power-on of logical partitions in a logical partition computer system is disclosed. An operator is allowed to enter a timed power-on value (TPO) value representing a time to boot one or more of the logical partitions. The TPO value for each of the logical partitions is then stored in nonvolatile memory. The system time is then periodically compared with each of the TPO values, and the corresponding partition is booted when the system time is greater than or equal to the TPO value.

Method for timed booting of logical partitions in a computer system in accordance with a preset schedule stored in nonvolatile memory

A distributed array processing system includes a bus divided into two portions or segments by a switch. One segment is connected to a processor and to a bus arbiter for controlling use of the bus. The bus arbiter provides one source of bus grant signals. A control register provides a second source of bus grant signals and additional signals for disabling the arbiter and actuating the switch. The control register is software controlled, i.e., it is loadable with data or control signals, under program control, to control use of the bus.

Program controlled bus arbitration for a distributed array processing

In a data processor having a paging system, a list is kept of the disk seek time when a page of information is brought into processor memory from a disk storage device. (Seek time is the time for moving the disk read-write head radially inward or outward to the next track that is to be accessed.) The average seek time for the pages in memory is calculated and is compared with a reference value of seek time. When the average reaches the reference, the pages in memory are reordered on the disk. This reordering takes place as the pages are bumped from memory in the normal process of paging, and the pages are relocated on the disk tracks in the physical order in which the pages were originally brought into memory. If approximately the same pages are fetched again in approximately the same sequence, the read-write head of the disk drive will be moved a shorter distance between successive disk accesses with reduced backtracking. The invention is particularly intended for a data processor of intermediate size that is large enough to use a paging system but small enough to use a disk drive that has an appreciable seek time.

Data processing system with reorganization of disk storage for improved

An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of data transfer (DTACK) timing. A late DTACK signal causes stretch of the clock controlled TXSTB transfer strobe to a length which will accommodate worst case memory access conditions of the asynchronous bus structure.

DMA asynchronous mode clock stretch

Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microprocessor before transferring control of the data and address busses to the DMAC and generates one or both of two data transfer strobe signals which instruct the memory to transfer contiguous bytes, contiguous high alternate order bytes, or contiguous low alternate order bytes, or both.

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Sandy Hook, CT, United States of America

Thomas A Kriz