Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Thomas A Asprey

Sean Tyler

Craig A Gleason

A method and apparatus for analyzing a circuit are described herein. The circuit may comprise at least two nodes, wherein each of the nodes has timing requirements associated therewith. An embodiment of the method comprises receiving a failure time of first node, wherein the failure time represents the time within which a signal must arrive at the first node from the second node in order to avoid a timing violation of the circuit. The second node is upstream of the first node. A potential slack is determined for the first node based on the failure time of the first node, wherein the potential slack is equal to the failure time minus the sum of the target time and the delay between the first node and the second node. The analysis is terminated if the potential slack is less than a first predetermined value. The target slack at the first node is determined, wherein the target slack is equal to the timing requirement of the first node minus the sum of the timing requirement of the second node and the delay between the first node and the second node. The timing requirement of the first node may be changed or relaxed if the target slack is less than a second predetermined value.

Method and system for performing timing analysis on a circuit

Systems and methods can be employed to determine one or more timing characteristics of a circuit design. In one embodiment, a system includes a calculator that provides an indication of slack for at least one node of a circuit design, the at least one node being capable of operating transparently and non-transparently. The indication of slack is determined based on a minimum of slack for paths that include the at least one node, regardless of path transparency.

System and method for determining timing characteristics of a circuit design

A system and method for improving cache memory write cycle timing in a microprocessor system, having static random access memory (SRAM) cache memory, using two out-of-phase clock signals and delayed variants thereof. The present invention includes the steps of sending a write address to the cache memory at a positive transition of the first out-of-phase clock signal that marks the beginning of the write cycle; causing a write control signal to be asserted at a time marked by next occurring positive transition of the second out-of-phase clock signal; sending the data to be written to the SRAM at a time marked by a drive clock signal; and ending the write cycle at a time marked by a end-write clock. The drive clock signal is provided by delaying the first out-of-phase clock signal. The amount of delay introduced in providing the drive clock signal is selected to allow the SRAM sufficient time to tri-state its drivers after receiving the write-control signal. The end write signal is provided by delaying the second out-of-phase clock signal. The amount of delay introduced in providing the end-write clock is selected to allow the SRAM sufficient time to read data to be written off of the data bus. The delay is introduced into the clock signals using printed circuit trace delay lines. The length of the printed circuit trace delay lines is selected such that the drive clock and end-write clock transitions occur at the optimum time.

System and method for performing high-sped cache memory writes

An integrated circuit output driver circuit is disclosed. The output driver varies the impedance of the driver circuit based upon the output voltage level present on the output pad. In that manner, the output driver circuit compensates for process variations and operating conditions. Two FETs are used in parallel to pull the voltage level of the output pad down. One FET is turned on and left on whenever a low voltage level in the output pad is desired. The other smaller FET is used to vary the total impedance of the driver by using feedback from the signal pad to sense when the pad voltage has reached a threshold level at that point the second FET is turned off.

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Boulder, CO, United States of America

Thomas A Asprey