Honeywell International Inc.

Thom Kreider

Mitch Fletcher

Jon Douglas Gilreath

Ron Strong

Paul D Kammann

Larry Jackson

Gary Warnica

Brian H Hamilton

Nicholas J Wilt

Paul Buchele

John F Dawson

Brian K Underhill

Terence J Marshall

Ronald E Strong

Brian Cornelius

Kirk Jones

Vince J Gavagan, Iv

Walter Edward Rupp

Vincent James Gavagan, Iv

Julee Clelland

Vince J Gavagan Iv

Terence Marshall

Embodiments of Reaction Wheel Assembly (RWA) systems are provided, which include multi-faceted bracket structures to which RWAs are mounted. In one embodiment, the RWA system includes a bracket structure, which is assembled from multiple (e.g., two to four) interchangeable panels. Each bracket panel may define or include a mount bracket to which an RWA is mounted. In certain embodiments, the bracket panels may include integral bearing cartridge features, which contain the spin bearings of the RWAs. The interchangeable panels may have interconnect features, which align and which possibly interlock to position the panels in a precise angular relationship when the multi-faceted bracket structure is assembled. In other embodiments wherein the bracket structure is assembled from two interchangeable panels or produced as a single piece, the multi-faceted bracket structure may have a peaked form factor supportive of two RWAs, which are mounted to the bracket structure in a back-to-back relationship.

Mass efficient reaction wheel assembly systems including multi-faceted bracket structures

A method for generating a pulse width modulation (PWM) signal, by a processor communicatively coupled to a system memory element, is provided. The method computes, by the processor, a coarse adjustment PWM output signal and a modified fine adjustment input signal, using a low speed clock rate; performs, by the processor, a fine adjustment to the coarse adjustment PWM output signal, using a high speed clock rate, based on the modified fine adjustment input signal; and generates an increased resolution PWM output signal, by the processor, based on the fine adjustment.

Systems and methods for generating high performance pulse width modulation (PWM) signals

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.

Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture

A rotor assembly for deployment within a momentum control device that enables near-zero revolutions per minute (RPM) sensing, and method for making same, are provided. The provided rotor assembly utilizes a magnet coupled to the rotor shaft and a stationary sensor element to detect magnetic flux from the magnet and derive reliable near zero RPM therefrom.

Near-zero revolutions per minute (RPM) sensing

A method for determining an updated rotor speed for a motor is provided. The method obtains, by a processor, a current rotor speed of the motor; determines a current mode for the motor, based on the current rotor speed, wherein the current mode comprises a low-speed mode, an intermediate speed mode, or a high-speed mode; detects one or more Hall events associated with a plurality of digital Hall Effect sensors coupled to the motor, based on the current mode; calculates, by the processor, a new rotor speed for the motor, based on the one or more Hall events and the current mode; and transmits the new rotor speed as a motor speed feedback signal, for digital speed control of the motor.

Methods and apparatus for multi-mode motor speed calculation using digital hall effect sensors

A method for calibrating a motor, the motor comprising a permanent magnet synchronous motor, is provided. The method generates a rotating magnetic field using a voltage vector, the rotating magnetic field configured to rotate at a constant angular velocity independent of an actual rotor position, and the rotating magnetic field rotating in a first direction; identifies, by a processor, timing data associated with a plurality of digital Hall effect sensors; computes, by the processor, accurate positions for each of the plurality of digital Hall effect sensors, using the timing data and the constant angular velocity; creates a reference table in system memory, by the processor, the reference table comprising the accurate positions; and during operation of the motor, calculates accurate angular velocity values for the motor, using the reference table.

Methods and systems for calibration of a motor

A printed circuit board assembly (PCBA) may include a printed circuit board (PCB), a socket mechanically and electrically coupled to the PCB, and an integrated circuit package electrically coupled to the socket. The PCBA also may include a thermal cover comprising a thermally conductive material and a thermal strap thermally coupled to the thermal cover. The thermal cover may be thermally coupled to the integrated circuit package and mechanically urge the integrated circuit package in contact with the socket, and the thermal strap may include a thermally conductive material.

Printed circuit board assembly including conductive heat transfer

A method for using an access triggered architecture for a computer implemented application is provided. The method receives a set of data at a designated functional block associated with a system memory location; performs an operation at the designated functional block, using the set of data, to generate a result, wherein the operation is performed each time information is received at the designated functional block; and returns the generated result to the system memory location.

Methods and apparatus to use an access triggered computer architecture

Systems and methods are described for synchronizing data in a mobile platform. In one embodiment, a method for synchronizing data in a mobile platform is provided. The method includes: receiving a first synchronization signal at a first remote interface unit from a signal generator; receiving a second synchronization signal at a second remote interface unit from the signal generator; and executing a synchronization state machine of the first and second remote interface units based on the first and second synchronization signals to synchronize outputs of the first and second remote interface units.

Integrated avionics systems and methods

A method for performing high-integrity data transmission is provided. The method obtains a first set of data at a first transmitter and a second set of data at a second transmitter; develops a first key for the obtained first set of data and a second key for the obtained second set of data; and when the first key matches the second key, provides a receiver indication of validity of the first set of data. In certain embodiments, the method stores the first key and the second key within a predetermined window of time. In some embodiments, when the first key matches the second key, the method also synchronizes operation of the first transmitter and the second transmitter.

Methods and apparatus for high-integrity data transfer with preemptive blocking

Devices systems and methods are provided for providing a deterministic remote interface unit (RIU) based on a finite state machine. The RIU emulator uses a sequence controller that is configured to receive a synchronization input and to execute a fixed list of unconditional commands in an invariable order of execution based solely upon the synchronization input. The RIU emulator also uses pre-defined or pre-certified data structures that are specific to one or more interface devices to successfully execute the at least one unconditional command of the plurality when encountered in the invariable order. As such, peripheral devices may be added, removed or updated without recertification by merely inserting pre-certified data structures into memory or deleting them.

Deterministic remote interface unit emulator

Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

Universal functionality module

Methods and systems are provided for reducing angular velocity of a vehicle using a gyroscope array. A method comprises dithering a gyroscope of the gyroscope array, obtaining current through a gimbal motor of the gyroscope while dithering the gyroscope, determining a gimbal rate command to reduce angular velocity of the vehicle based on the current through the gimbal motor obtained while dithering the gyroscope, and operating the gimbal motor of the gyroscope based on the gimbal rate command.

Methods and systems for reducing angular velocity using a gyroscope array

A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.

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Peoria, AZ, United States of America

Thom Kreider