International Business Machines Corporation

Thoi Nguyen

Robert Christopher Dixon

Louis Bennie Capps, Jr

Gary Dean Anderson

Hoa Cong Nguyen

Roger Donell Weekly

Gary Franklin Goth

Van Hoa Lee

Bret Peter Elison

Terrance Wayne Kueper

Ronald Xavier Arroyo

Kenneth A Bird

William A Ciarfella

Keith Alan Cox

Mark Edward Dean

James J Molloy

Richard Nicholas Iachetta, Jr

Stanley Dyer

Donald Lee West

Khuong Huu Pham

William F Voit, Jr

Allan Rowe Steel

Yashwant Sakarchand Kothari

Josefina Santiago Drerup

David M Riherd

Tuan Hoang Nguyen

A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Method and system for managing peripheral connection wakeup in a processing system supporting multiple virtual machines

Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.

Systems and arrangements to assess thermal performance

In a computer system having a power supply, processor, and additional subcomponents that are powered by the power supply, a method for estimating the total power requirements of the system under a variety of operating modes and configurations. In an exemplary embodiment, information concerning power requirements for each subcomponent under its operating modes is stored within non-volatile memory within the subcomponents. This information is accessed by the processor during the boot sequence, and if the information is not available, substitute information is provided. The compiled information is tabulated to compute the estimated total power requirement of the current hardware configuration. A display of this information, along with configuration selection rules, enables the user to select alternative operating modes and configurations and to show the resulting estimated power requirements.

Method for estimating total power requirement in a computer system

A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan.

Multiple fan sensing circuit and method for monitoring multiple cooling fans utilizing a single fan sense input

An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.

Apparatus for memory bus tuning and methods therefor

An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus. The test state applied to the check bits line varies from the check bit state that would be generated by the ECC unit of the computer system upon receiving the test state that is applied to the data bit lines.

Method and apparatus for ECC logic test

A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.

Circuit for detecting improper bus termination on a SCSI bus

A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.

Switching system for optimization of signal reflection

A method and apparatus for detecting and identifying the attributes of level-2 (L2) memory cache modules in a computer system. An ID Module is attached to each L2 cache memory module containing memory attribute information such as size, presence or absence of parity, synchronous or asynchronous access ability, electrical timing, etc. The information is accessible using a parallel or serial interface.

Method and apparatus for detecting the presence and identification of

A connector on a printed circuit board of a computer system is reused to reduce a number of connectors utilized on a motherboard of a computer system. By recognizing that some signals are common between a programming application performed during a manufacturing process and a second application performed while the computer system is a normal customer operation, the connector may be used to provide data values during both the manufacturing process and normal customer operation. Stated another way, data signals used to drive programmed data during the manufacturing process may be re-used to provide serial data to an input/output device during normal customer operation.

Data processing system and method for optimizing connector usage

A method and apparatus for providing a memory system having error checking and correction (ECC) capability, and parity error detection capability on the same memory card, and user selection of either capability using the same type of memory modules. A memory controller having programmable configuration registers is provide for user selection of either ECC or parity capability. Eight-byte Dual in-line Memory Modules are used to provide 64-bit data which allows the memory controller to use eight extra bits for both ECC and parity capability.

Method and apparatus for optimizing ECC memory performance

A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Growing community of inventors

Austin, TX, United States of America

Thoi Nguyen