Intel Corporation

Thoe Michaelos

Marko Radosavljevic

Leonard P Guler

Nicole K Thomas

Gilbert W Dewey

Matthew V Metz

Van H Le

Abhishek A Sharma

Noriyuki Sato

Charles C Kuo

Bernhard Sell

Hui Jae Yoo

Scott Bruce Clendenning

Elliot Tan

Travis W LaJoie

Michael Harper

I-Cheng Tung

Sudarat Lee

Sarah Atanasov

Tobias Brown-Heft

Eric Charles Mattson

Chieh-jen Ku

Charles Mokhtarzadeh

Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

Plug and recess process for dual metal gate on stacked nanoribbon devices

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Transistors, memory cells, and arrangements thereof

Growing community of inventors

Portland, OR, United States of America

Thoe Michaelos