Honeywell G.m.b.h.

Tho T Vu

Roderick D Nelson

Peter C Roberts

Andrzej Peczalski

James D Joseph

Kang W Lee

Danh N Tran

A feedback source coupled FET logic (FSCL) circuit having an internal reference voltage provided by the output of one FET of a pair of FET's, connected via a source follower FET to the input of the other FET of the pair. FSCL logic circuitry has advantages over known source coupled FET logic (SCFL) circuitry in that FSCL has higher density of functions for a given area of integrated circuitry, lower voltage drift with temperature change, higher voltage gain, higher noise margin, and larger fanout loading. The output of one FET, via a source follower FET, is connected to the input of the other FET of the pair.

Feedback source coupled FET logic

Exclusive diode-FET logic circuitry capable of providing functional programmable logic array output logic signals within one-gate delay from an initial input logic signal, and functional read-only memory output data signals within two- or three-gate delay from an initial input address signal. The OR and AND functions of the circuit are performed by diode configurations thus resulting in high packing density, easy logic array programming, low power dissipation, and high speed operations. The invention may utilize Schottky diodes and metal semiconductor FETs thereby allowing the implementation of high speed gallium arsenide integrated circuit technology.

Diode-FET logic circuitry

A GaAs SCFL RAM having a unique three-voltage-level write circuit, direct-read circuitry with only one gate delay, diode-coupled FET logic cells, and peripheral circuitry with SCFL gates. The memory module architecture and plan of the RAM allow for several design options which may include 1K.times.16 and 16K.times.1 memory configurations. The RAM incorporates strobe circuitry for powering down selected memory modules, without loss of data, thus reducing power dissipation. The SCFL circuitry of the RAM functions with closely matched complementary signals for fast switching with minimum current spiking. The RAM has a wide range of threshold voltage tolerance, excellent noise margin, and a very high level of radioactive radiation hardness.

GaAs SCFL RAM

A semiconductor memory cell includes cross coupled bipolar transistors operated in the forward current mode with power fed to the base of the transistor through Schottky diodes from separate word lines. Bit lines are connected to the transistors' emitters and a high differential current is sensed between the bit lines during read operations. No resistors are included within the cell.

Semiconductor memory cell including cross-coupled bipolar transistors

A very high speed, low power integrated interface circuit using GaAs or InP technology is provided for converting small digital voltage swings to larger swings which are particularly suitable for analog control signals. The preferred embodiments employ solely depletion mode MESFETS and Schottky diodes in Schottky diode field effect logic (SDFL) configurations.

GaAs level-shift logic interface circuit

A switching network for a GaAs semiconductor circuit employing four FETs. The FETs are configured in a ring pattern which is connected to two matched current sources. Also disclosed is a sample-and-hold circuit employing such a switching network.

Switching network

An OR logic function is provided in at least two separate circuit branches by diodes in parallel summing current at a first logic node and a first circuit branch and diodes in parallel summing current at a second logic node in a second current branch. An AND logic function is performed at a third logic node by using additional diodes connected in parallel at the third logic node so as to share current passing through the third logic node, with the logic conditions at the first and second logic nodes serving as the inputs to the AND logic function. The logic condition at the third logic node is applied to the gate of a switching FET. The switching FET is conveniently employed to invert the logic condition at the third logic node. The invention is particularly suited for use with MESFET logic families using gallium arsenide (GaAs) substrates.

Multiple input and multiple output or/and circuit

An OR-AND logic circuit includes a plurality of OR gates wherein each OR gate includes a plurality of source coupled FETs and the inputs to each OR gate are the control gates of the FETs. A logic node serves as the output for each OR gate. A unidirectional current conducting means, such as a Schottky diode, is connected to each output logic node of each OR gate. One terminal of each unidirectional current conducting means is connected to a common logic node. Current passing through a load means passes through the common logic node and is divided among the unidirectional current conducting means so that a logical AND function is provided at the common logic node with the logic condition at the output logic nodes of the OR gates serving as the inputs to the AND gate. Multiple levels of such OR-AND circuits can be provided with the AND output of one level serving as the input to an OR gate of the next stage.

Multiple input OR-AND circuit for FET logic

Two MESFETS with the drain of one connected to the source of the other are driven in complementary fashion by a single inverter using a third MESFET and a voltage level shifter, in response to digital signals input to the inverter. Means for selectively disconnecting the power supply from the inverter to place the circuit in a low power, standby mode is provided. Depletion and enhancement mode MESFET configurations of the circuit are disclosed.

Digital circuit using MESFETS

An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. It is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configuration for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.

Semiconductor memory

A bipolar OR logic circuit includes input diodes directly connected to a switching transistor. A first current source is coupled to the transistor's emitter and a load is directly connected to and between the collector and a voltage reference point. A second current source, connected to the transistor's base, sets the switching point of the transistor. The output is taken at the collector. A second bipolar transistor can be cross coupled to the first transistor to provide a voltage reference for the base of the first transistor and/or shift the logic level by taking the output at the emitter of the second transistor.

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Fridley, MN, United States of America

Tho T Vu