Cypress Semiconductor Corporation

Avalanche Technology, Inc.

Thinh Tran

Joseph Tzou

Suresh Parameswaran

Jun Li

Morgan Andrew Whately

Ebrahim Abedifard

Gabriel M Li

Edward L Grivna

Mourad El Baraji

Derwin W Mattos

Bruce Barbara

Jithender Majjiga

Christopher Lee

The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

Magnetic memory read circuit and calibration method therefor

The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.

Nonvolatile memory sensing circuit including variable current source

The present invention is directed to a nonvolatile memory device that includes a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a first target resistor and a balancing resistor connected in series between the first input node and the first input terminal; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a second target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.

Fast programming of magnetic random access memory (MRAM)

A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.

Access methods and circuits for memory devices having multiple banks

An integrated circuit (IC) device can include a memory array section comprising a plurality of memory arrays that each include memory cells for storing data values; a data path section having switching circuits configured to enable data paths between the memory arrays and a plurality of input/outputs (I/Os) of the IC device; and a power fill control circuit configured to activate power-fill circuits in the IC device to perform non-mission mode operations that consume current, the amount of non-mission mode operations varying in response to mission mode circuit activity in the IC device; wherein mission mode circuit activity includes circuit activity resulting from a user input to the IC device.

Power management system for high traffic integrated circuit

A memory device can include a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array portion; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses corresponding to the write data of the forwarding circuit.

Data forwarding circuits and methods for memory devices with write latency

A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.

A memory device can include first sense amplifiers coupled to bit lines of a memory array in a first access period and de-coupled from the bit lines in a first sense period, the first sense amplifiers configured to amplify data signals from the memory array in the first sense period; and second sense amplifiers coupled to the bit lines in a second access period that follows the first access period and configured to amplify data signals from the memory cell array in a second sense period that overlaps the first sense period.

High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same

A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.

Memory device data latency circuits and methods

A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Serial interface devices, systems and methods

A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period.

Memory device and method

A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Memory system and method

An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

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Palo Alto, CA, United States of America

Thinh Tran