Infineon Technologies Ag

Siemens Aktiengesellschaft

Kabushiki Kaisha Toshiba

Qimonda Ag

Thilo Schaffroth

Helmut Schneider

Florian Schamberger

Robert Kaiser

Thomas Hein

Martin Brox

Wolfgang Anton Spirkl

Peter Gregorius

Hermann Ruckerbauer

Helmut Fischer

Johannes Stecker

Naokazu Miyawaki

Mike A Killian

Martin Maier

Ralf Schedel

Franz Freimuth

Alessandro Minzoni

Peter Beer

Gunnar H Krause

Ralf Schneider

Joachim Schnabel

J&uuml;rgen Lindolf

Eckhard Brass

Ioannis Chrissostomidis

Rudiger Brede

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Multi-port DRAM architecture for accessing different memory partitions

A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.

Semiconductor device chip, semiconductor device system, and method

A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.

System for testing an integrated circuit using multiple test modes

A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

Evaluation circuit for a DRAM

A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a selected connecting pin. Since there are normally no unused connecting pins, in, for example, present-day large scale integrated components, the connected module is disconnected from a selected connecting pin for a specific time period, and the divided measurement voltage is passed to the connecting pin. This is done by use of a controller, which operates appropriate switches. This method is preferably used for memory components such as DRAM, SRAM etc.

Method and semiconductor component having a device for determining an internal voltage

A self-test device serves for carrying out a self-test of an integrated circuit. An output of the self-test device is connected to a contact-making point of the circuit, which serves for external contact-making and which is connected to an input of a circuit unit of the integrated circuit to be tested. The self-test device feeds a test signal through the contact-making point to the circuit unit.

Integrated circuit having a self-test device

An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.

Integrated circuit having a timing circuit, and method for adjustment of an output signal from the timing circuit

The invention relates to a configuration for fuse initialization, in which the fuse initialization signals bFPUP, FPUN are carried on a total of two lines to the individual fuse banks, and are sent back with a time delay.

Configuration for fuse initialization

A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that are supplied with a normal standard supply voltage, thick oxide transistors to which an increased supply voltage is applied to compensate for voltage and technological fluctuations.

Circuit configuration for generating sense amplifier control signals

In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Semiconductor circuit configuration

A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

Method for testing a multiplicity of word lines of a semiconductor memory configuration

A method of testing leakage current at a contact-making point in an integrated circuit includes applying a test potential to the contact-making point through an output of an application device. The output of the application device is connected to a high impedance or is isolated from the contact-making point. The potential at the contact-making point is determined as a measure of the leakage current being produced.

Method of testing leakage current at a contact-making point in an integrated circuit by determining a potential at the contact-making point

An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

Adjustable delay circuit

A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an 'internal' operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Growing community of inventors

Röhrmoos, Germany

Thilo Schaffroth