Nantero, Inc.

Semiconductor Components Industries, LLC

Thierry Yao

Thomas Rueckes

Eliodor G Ghenciu

J Thomas Kocab

Weize Chen

Johan Camiel Julia Janssens

Moshe Agam

Mark Griswold

Jaroslav Pjencak

Thomas Kocab

Tom Kocab

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Isolation structure for semiconductor device having self-biasing buried layer and method therefor

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

Two-terminal switching devices comprising coated nanotube elements

A Laterally Diffused MOSFET (LDMOS) device architecture particularly suitable for use in tight pitch environments such as for line drivers in an integrated memory application. In one embodiment, an illustrative high-voltage MOSFET device includes: a body (a semiconductor of a first conductivity type), a source region (a semiconductor of a second conductivity type) at a source active area and positioned within or adjacent to the body, a drift region (a lightly-doped semiconductor of the second conductivity type) positioned adjacent to the body, and a gate overlying at least a portion of the body and at least a portion of the drift region to form a controllable channel between the source region and the drift region. To increase the drain breakdown voltage, a width dimension of the drift region is formed to be sufficiently small for a depletion zone to extend across a full width of the drift region.

Laterally diffused MOSFET for embedded memory applications

Resistive materials comprising mixed nanoscopic particles and carbon nanotubes

Two-terminal switching device using a composite material of nanoscopic particles and carbon nanotubes

Switching materials comprising mixed nanoscopic particles and carbon nanotubes and methods of making and using the same

Switching materials comprising mixed nanoscopic particles and carbon nanotubes and method of making and using the same

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Portland, OR, United States of America

Thierry Yao