Skyworks Solutions, Inc.

Stmicroelectronics S.a.

Thierry Lepley

Michel Harrand

Jean-Marc Daveau

Thomas A D Riley

José Sanches

Marco Cornero

Miguel Santana

Philippe Guillaume

Pierre Paulin

Tadeuse A Kwasniewski

Thomas Atkin Riley

A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Signal processor executing variable size instructions using parallel memory banks that do not include any no-operation type codes, and corresponding method

A delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold. Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.

Multiple stage delta sigma modulator

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Grenoble, France

Thierry Lepley