Luxtera, Inc.

Other

Luxtern, Inc.

Gunn III, Lawrence C.

Thierry J Pinguet

Lawrence Cary Gunn, Iii

Maxime Jean Rattier

Attila Mekis

Steffen Gloeckner

Mark D Peterson

Peter De Dobbelaere

Gianlorenzo Masini

Sherif Abdalla

Mark Harrison

Daniel Kucharski

Alexander G Dickinson

Bing Li

Jeremy Witzens

Peter DeDobbelaere

Roger Koumans

John Andrew Guckenberger

Guo Li

Kosei Yokoyama

Subal Sahni

Giovanni Capellini

Ali Ayazi

Thiruvikraman Sadagopan

Myles A Sussman

Roman Malendevich

Behnam Analui

Sina Mirsaidi

Yannick De Koninck

David Press

Zhen-Li Ji

David L R Press

Lawrence C Gunn

John Guckenberger

Guckenberger John

Lawrence C Gunn Iii

Guo Liang Li

Lawrence C Iii Gunn

C Gunn Iii Lawrence

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Method and system for monolithic integration of photonics and electronics in CMOS processes

Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include in an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have fingers of p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide. Contacts may be formed on the fingers of p-doped and n-doped regions. The fingers of p-doped and n-doped regions may be arranged symmetrically about the PN junction waveguide or staggered along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

Method and system for a low parasitic silicon high-speed phase modulator using PN finger waveguides

Methods and systems for optoelectronics transceivers of a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers, which may include a guard ring. A CW optical signal may be received from a laser source via optical couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

Method and system for optoelectronics transceivers integrated on a CMOS chip

Method and system for a low parasitic silicon high-speed phase modulator using raised fingers along a PN junction waveguide

A transceiver comprising a chip, a semiconductor laser bonded to the chip, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via a, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip.

Integrated transceiver with lightpipe coupler

A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of a CMOS photonic chip comprising photonic, electronic, and optoelectronic devices. The devices may be integrated in a front surface of the chip and one or more optical couplers may receive the optical signals in the front surface of the chip. The optical signals may be coupled into the back surface of the chip via one or more optical fibers and/or optical source assemblies. The optical signals may be coupled to the grating couplers via a light path etched in the chip, which may be refilled with silicon dioxide. The chip may be flip-chip bonded to a packaging substrate. Optical signals may be reflected back to the grating couplers via metal reflectors, which may be integrated in dielectric layers on the chip.

Method and system for coupling optical signals into silicon optoelectronic chips

Methods and systems for a chip-on-wafer-on-substrate assembly are disclosed and may include in an optical communication system comprising an electronics die and a substrate. The electronics die is bonded to a first surface of a photonic interposer and the substrate is coupled to a second surface of the photonic interposer opposite to the first surface. An optical fiber and a light source assembly are coupled to the second surface of the interposer in one or more cavities formed in the substrate. A continuous wave (CW) optical signal may be received in the photonic interposer from the light source assembly, and a modulated optical signal may be communicated between the optical fiber and photonic interposer. The received CW optical signal may be coupled to an optical waveguide in the photonic interposer using a grating coupler.

Method and system for a chip-on-wafer-on-substrate assembly

Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via optical couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide, and portions of the p-doped and n-doped regions may be removed. Contacts may be formed on remaining portions of the p-doped and n-doped regions. Portions of the p-doped and n-doped regions may be removed symmetrically about the PN junction waveguide. Portions of the p-doped and n-doped regions may be removed in a staggered fashion along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

Method and system for a low parasitic silicon high-speed phase modulator with intermittent P-and N-doped raised fingers

A transceiver comprising a chip, a semiconductor laser, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via a light pipe with a sloped reflective surface coupled to the chip, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip. The light pipe may be a planar lightwave circuit (PLC).

Method and system for a low parasitic silicon high-speed phase modulator having raised fingers perpendicular to the PN junction

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Cardif-By-The-Sea, CA, United States of America

Thierry J Pinguet