Thomson-csf

Sgs-thomson Microelectronics Limited

Ipanema Technologies

Ipanema Technologies S.a.

Thierry Grenot

Marcello Coppola

Neil Richards

Robert John Simpson

Pascal Moniot

Pierre Dumas

David Mouen Makoua

Peter Thompson

Michel Delattre

Marc Bavant

Pierre Lagoutte

Bernard Imbert

Francois Tarbouriech

Colette Vivant

Jacques Provost

Dominique Bolot

Jean-Yves Leclerc

Francois Lecerf

Florian Bonnet

Jean Caillemer

Jacques Brisson

Francedillaois Tarbouriech

Dominique Conti

Patrick Letourneur

The invention relates to a method for optimising the sharing of a plurality of network resources between a plurality of data flows generated by a plurality of applications, said flows being able to take a number n of paths [ABi], i=1 to n, linking at least one site A and at least one site B in a telecommunications network (). The method according to the invention consists in modifying the distribution of the flows on the paths [ABi], i=1 to n, in such a way as to balance the Effective Demand Densities of the available paths.

Method for optimising the sharing of a plurality of network resources between a plurality of application flows

The invention relates to a method for remotely controlling the congestion of meshed flow exchanged in a packet mode telecommunication network between a number N of central sites Cprovided with flow management devices and a number M of remote sites Ddevoid of such devices. According to the invention, said active devices of central sites Cexchange between them information intended specifically for the management of flows exchanged between each of the central sites Cand each of the remote sites D.

Method and device for remotely controlling the congestion of meshed flow in a packet mode telecommunication network

A dynamic optimization process of a quality of service (QoS) in a data transmission packet network. The data transmission packet network includes a plurality of sources and a plurality of destinations connected to a transit network by a plurality of access networks. Each source is configured to send data at a maximum data rate and each destination is configured to receive a maximum transmission data rate. The sources each includes a classification and a control device configured to control a transmission data rate of transmitted data. The process is characterized in that the absolute transfer delay period, the jitter, the output of the exchanged data and the losses between each source S and each destination D are measured, and the classification and control means of the output are monitored.

Dynamic optimization process of quality service in a data transmission network

The invention relates to a system and non-intrusive method for measuring loss rates and transfer durations for data flows that are sent by a telecommunication network in packet mode. The inventive method is characterized in that it comprises the following steps: classification of the data packet in a homogeneous flow; calculation of an identification signature for each data packet; counting of the packets in the flow; measurement of unidirectional transfer times per flow or information flow group and measurement of the loss rate for said packets.

System and method for measuring the transfer durations and loss rates in high volume telecommunication networks

A device for ATM cell switching having failure tolerance. The device is divided into two types of equipment modules. The first type includes connecting modules while the second type includes two branching and managing modules, one operating in an active mode while the other operates in a passive mode. An accessing device is implanted in each connector. Devices to execute the ATM layer function are almost identically implanted in each connector and in each of the two branching and managing modules. A supervision bus connects both types of modules to ensure quick and automatic reconfiguration of the device in case of failure in one of its components. The supervising bus is of simple configuration and only serves to carry, under the control of the managing module, signals indicative of the master and slave managing means as well as a signal indicative of the active branching module.

Device for ATM cell switching, with failure tolerance

An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.

Congestion avoidance in an ATM switch

An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

ATM switch

An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Cell queue formation in an ATM switch

A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.

ATM switch flow control

An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.

The disclosed device, placed within an ATM packet switch, is of the type comprising a multiplexer associated with a specified number of input and output buffers and a device to control the internal flows of ATM cells informing the input buffers of the state of congestion of the output buffers. This device further comprises means to convert the flow of sporadic point-to-multipoint cells, arriving at the input of the input buffers, into a regular flow of point-to-multipoint cells towards the multiplexer irrespective of the outgoing direction taken by the cells and independently for each input.

Device to regulate the flow of ATM cells within an ATM packet switch

The method enables the control of congestion in sporadic exchanges of packets of data in a digital transmission network. Each packet is formed by a header enabling it to be identified and to be guided through virtual channels and by a part containing information elements to be conveyed. The method includes detecting, at each node of the network, channels that are congested, and, on nodes upline with respect to each congested virtual channel detected, transmitting a congestion indicator to stop connections on the congested virtual channels so long as the congestion observed by a node on the congested virtual channels has not been cleared.

Method and device for the control of congestion in sporadic exchanges of

The method of identifying, in a memory space of the node, a virtual circuit of a network to which the cell belongs, on the basis of virtual path numbers VPI and virtual channel numbers VCI contained in the header of the cell. This method includes

Method and device for the translation of a cell header applied to the

A method for the routing of a packet of data in a digital transmission network where each packet is formed by a header, enabling this packet to be identified and guided, and a part containing information elements to be conveyed. This method consists, at each node of the network, of a first step for extracting, from the header, the address of a word of a memory containing the information elements needed to identify the header and to guide the data elements conveyed by the packet coming into the node and a second step for creating, according to the header of the incoming packet and the information elements contained in the word of the memory, a new address designating a memory zone containing at least one new header and the information on the outgoing direction of the packet or packets coming out of the node. The method can be applied to digital transmission networks where it is necessary to identify and route packets of data.

Method for the routing of a packet of data in a digital transmission

A transit switch of an asynchronous network, notably an ATM network, for the handling of information elements in the form of packets having a header part for the identification of a destination and a information element part, having a plurality of input junctors supplied with packets by a plurality of associated input channels, there are also a plurality of output junctors connected to the input junctors by a synchronous bus, a bus allocator circuit is connected to the input junctors and to the bus. The switch is arranged so that each input junctor transfers a received packet to at least one output junctor which is identified from the header part of the packet to be transferred.

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Clamart, France

Thierry Grenot