Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Microsoft Technology Licensing, LLC

Thierry Fevrier

David W Engler

Joseph Foster

Dwight D Riley

David F Heinrich

Vincent Hung Nguyen

Justin Haanbyull Park

Gary Belgrave Gostin

Mark Edward Shaw

Richard W Adkisson

Craig William Warner

Conor J Cunningham

James Alexander Fuxa

William C Hallowell

Taciano Perez

Michael Alex Schroeder

Huai-Ter Victor Chong

Arad Rostampour

Joe Perry Cowan

Carlos Haas

Larry N McMahan

Thiago Silva

David M Binford

Mark S Fletcher

Louis Laborde

Spencer A Frink

Philp Garcia

Computing resource management is improved during fast sorting using vector instructions. The process includes: determining a pivot value and a pivot position in a data set (e.g., by sampling with vectors and determining the sample median), determining whether moving data in the sampled portion may be avoided (e.g., if it is constant-valued or already sorted) and, leveraging that determination to possibly avoid unnecessary data movement, sorting the data set. Some examples further determine the microarchitecture version of the computing device performing the sorting and select an implementation of sorting instruction that is tuned for that microarchitecture version (e.g., based on the number of vector registers and motherboard cache configuration). Some examples leverage a soft 3-way quicksort by finding data elements adjacent to the pivot position that also have the pivot value and adding a partition boundary at the end of the set of same-valued data elements.

Computing resource management with fast sorting using vector instructions

Examples disclosed herein relate to updating memory management information to boot an electronic device from a reduced power mode. In one implementation, prior to entering a reduced power mode, an electronic device creates a snapshot of instructions in a logically volatile partition of a partitioned persistent memory and manage the snapshot as a logically persistent partition. Prior to entering a resume mode, the electronic device updates memory management information to remap a portion of the partitioned memory resource including the snapshot to be managed as a logically volatile partition. The electronic device may resume execution from the snapshot.

Update memory management information to boot an electronic device from a reduced power mode

An example device in accordance with an aspect of the present disclosure includes a plurality of memory segments corresponding to at least one memory channel of a computing system that is to receive a memory module. A performance attribute of an Advanced Configuration and Power Interface (ACPI) table is set to indicate performance of at least one of the plurality of memory segments, and is usable for memory allocation by an operating system memory manager.

Performance attributes for memory

A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

Data copy to non-volatile memory

A system for achieving memory persistence includes a volatile memory, a non-volatile memory, and a processor. The processor may indicate a volatile memory range for the processor to backup, and open a memory window for the processor to access. The system further includes a power supply. The power supply may provide power for the processor to backup the memory range of the volatile memory. The processor may, responsive to an occurrence of a backup event, initiate a memory transfer using the opened memory window. The memory transfer uses the processor to move the memory range of the volatile memory to a memory region of the non-volatile memory.

Memory persistence from a volatile memory to a non-volatile memory

According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

Dual-port non-volatile dual in-line memory modules

A computing device having firmware, an uninterruptible power supply (UPS), and a memory module with volatile memory. Firmware tasks are prioritized to elevate tasks associated with the copying of the contents of the volatile memory to the nonvolatile memory external to the memory module during the loss of main or primary power.

Prioritizing tasks for copying to nonvolatile memory

According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

Replicating data using dual-port non-volatile dual in-line memory modules

A technique includes writing a first count value associated with a first timestamp counter to a first memory local to the first timestamp counter. The technique includes writing a second count value associated with a second timestamp counter to a second memory local to the second timestamp counter. The timestamp counters are synchronized based at least in part on the first and second count values.

Synchronizing timestamp counters

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Communication among partitioned devices

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Gold River, CA, United States of America

Thierry Fevrier