Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie

Thierry Collette

Fabien Clermidy

Nicolas Ventroux

Raphaël David

Frédéric Blanc

Michel Harrand

Hassane Essafi

Vincent David

Stéphane Louise

Laurent Letellier

Renaud Schmit

Stéphane Chevobbe

Jean-Pierre Guerin

Hassane Es-Safi

David Vincent

Frederic Blanc

Mickaël Guibert

Jean-Francedillaois Larue

Jean Rebillat

Josef Kaiser

A system including a plurality of processing units for executing tasks in parallel and a communication network. The processing units are organized into clusters of units, each cluster comprising a local memory. The system includes means for statically allocating tasks to each cluster of units, so that a task of an application is processed by the same cluster of units from one execution to another. Each cluster includes cluster management means for allocating tasks to each of its processing units and space in the local memory for executing them, so that a given task of an application may not be processed by the same processing unit from one execution to another. The cluster management means includes means for managing the tasks, means for managing the processing units, means for managing the local memory and means for managing the communications involving its processing units. The management means operate simultaneously and cooperatively.

Statically allocating set of tasks to particular cluster and dynamically allocating each task to different processing units within cluster

The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU, . . . , APUN-) that are optimized for fast processing of certain operations, a memory space (SMS) shared by the auxiliary calculation units (APU, . . . , APUN-) via an internal network and a unit (ACU) for controlling and assigning the auxiliary resources. The various elements of the system are arranged in such a manner that communication between the various auxiliary calculation units (APU, . . . , APUN-) or between those auxiliary calculation units (APU, . . . , APUN-) and the central processor core (SPP) is effected via the shared memory space (SMS) and the internal network.

Method and system for conducting intensive multitask and multiflow calculation in real-time

The invention relates to a method for scheduling the processing of tasks and to the associated device, the processing of a task comprising a step for configuring resources required for executing the task and a step for executing the task on the thereby configured resources, the method comprising a selection () of at least one level of independent tasks to be processed in accordance with an order of precedence and a step for sorting () out the tasks of the level of tasks to be processed in order to define, an order of priority in the processing of the tasks, depending on the number of resources required for processing the tasks on the one hand and on a time characteristic of the tasks on the other hand.

Method for configuring resources and scheduling task processing with an order of precedence

A reconfigurable control system based on duplication of cells, in which each of these cells corresponds to a place on a Petri graph, and in that the configuration models the topology of the associated Petri graph.

Reconfigurable control system based on hardware implementation of Petri graphs

The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.

Component with a dynamically reconfigurable architecture

Reconfiguration method applicable to an array of identical functional elements

This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.

Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network

The invention relates to a process for controlling the circulation of messages in a ring network, in which the data are consecutively supplied, which ensures a consistency of the circulating messages. It also relates to an interconnection system for performing this process. This system comprises a plurality of processors (P0, . . . , Pn) connected on a ring network by means of in each case a cell (C0, . . . , Cn) ensuring the transmission and reception of messages circulating in the ring, a reception module (R0, . . . , Rn) able to store the messages intended for the processor and a transmission module (E0, . . . En) able to store the messages to be supplied to the network.

Interconnection process and system for the control of messages in an

Parallel processor system

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Palaiseau, France

Thierry Collette