Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Thierry Cassagnes

Hugues Beaulaton

Laurent Cornibert

Douglas Alan Garrity

Philippe Lance

Valerie Bernon-Enjalbert

Ira G Miller

Didier Salle

Gerhard Trauth

Volker Dietmar Wahl

Brandt Braswell

Aaron A Geisberger

Hao Li

Gilles Montoriol

Margaret Leslie Kniffin

Pierre Pascal Savary

David R LoCascio

Yean Ling Teo

Christophe Landez

Matthijs Pardoen

Robert Gach

Marianne Maleyran

Akbar Ghazinour

Valérie Bernon-Enjalbert

Stephane Colomines

Stéphane Colomines

Christopher J Cavanagh

Mohammad Nlzam U Kablr

An integrated device includes a MEMS device, such as a gyroscope, having a movable mass spaced apart from a substrate, the movable mass being configured to oscillate in a drive direction relative to the substrate. The integrated device further comprises an integrated circuit (IC) die having a surface coupled with the MEMS device such that the movable mass is interposed between the substrate and the surface of the IC die. An electrode structure is formed on the surface of the IC die, the electrode structure including a plurality of electrode segments vertically spaced apart from the movable mass. Openings extend through the movable mass and the electrode segments overlie the openings. Suitably selected electrode segments can be activated to electrostatically attract the movable mass toward sense electrodes vertically spaced apart from the MEMS to reduce quadrature motion of the movable mass.

Segmented electrode structure for quadrature reduction in an integrated device

Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

In-band beating removal for a MEMS gyroscope

A drive circuitry for a vibration gyroscope is described. The drive circuitry comprises a digital phase shifter, a variable gain amplifier and a pulse signal generator arranged to generate a digital pulse signal having a frequency substantially equal to a drive frequency of the vibration gyroscope. A controller is arranged to connect drive actuation units of the vibration gyroscope to outputs of the pulse signal generator during a first start-up time period, to outputs of the digital phase shifter during a second start-up time period, and to outputs of the variable gain amplifier during a measurement time period. Furthermore, a vibration gyroscope device and a method of driving a vibration gyroscope are described.

Drive circuitry and method for a vibration gyroscope

A system comprises a mechanical resonator; an analog circuit operably coupled to the mechanical resonator; the analog circuit arranged to receive a mechanical resonator measurement signal and to output a mechanical resonator actuation signal to the mechanical resonator; and a digital actuator operably coupled to the analog circuit and configured to provide a frequency sweep of signals to the analog circuit that induces movement of the mechanical resonator.

System comprising a mechanical resonator and method therefor

A drive-mode oscillator module generates at least one proof-mass drive signal for use within a micro-electro-mechanical system (MEMS) device. The drive-mode oscillator module comprises at least one gain control component arranged to receive at least one proof-mass motion measurement signal, and to generate a digital modulation control signal based at least partly on the at least one proof-mass motion measurement signal, and at least one modulation component arranged to receive the digital amplitude modulation control signal, and to output at least one proof-mass drive signal. The at least one modulation component is arranged to digitally modulate the at least one proof-mass drive signal based at least partly on the received digital amplitude modulation control signal.

Method and apparatus for generating a proof-mass drive signal

A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.

PLL system and method for controlling a gain of a VCO circuit

An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Integrated circuit comprising frequency generation circuitry for controlling a frequency source

Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.

System and method for communicating on an electrical bus

A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.

Fault management for a communication bus

A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal

A pipelined analog to digital converter ('ADC') as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization ('DHS') stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Multi-channel analog to digital converter

An analog-to-digital (A/D) converter suitable for use with redundant signed digit (RSD) coverter stages is provided with an out-of-range (OOR) detection circuit. If an out-of-range input signal is detected, the detection circuit identifies the OOR condition so that the converter can take remedial action. Examples of remedial action may include adjusting the gain of one or more converter stages, adjusting the analog input signal provided to one or more converter stages, and/or adjusting the digital output of the converter to reflect the OOR condition. The ORR detection circuit may receive its input from a converter stage that is distinct from the stage providing the most significant bit (MSB) of the digital output to preserve the resolution of the most significant bit.

Methods and apparatus for detecting out-of-range signals in an analog-to-digital converter

A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.

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Tournefeuille, France

Thierry Cassagnes