Advanced Micro Devices Corporation

Other

Motorola Corporation

Freescale Semiconductor,inc.

Cts Corporation

Thien T Nguyen

Mark I Gardner

Charles E May

Theodore E Lind

David J Weary

Joseph F Balascio

Jian Feng Chen

Bich-Yen Nguyen

Frederick N Hause

Voon-Yew Thean

Tab Allen Stephens

Michael D Turner

Brian J Goolsby

Derrick J Wristers

James Edward Vasek

Douglas J Dopp

Stephanie Annette Grahn

Michael Patrick McFee

Osefame Ewaleifoh

Valentin Medina, Jr

The present invention generally relates to methods and compositions for preventing or treating axonal and/or neuronal degeneration in a subject by administering a composition comprising a peptide that comprises the amino acid sequence Arginine-Glycine-Aspartate (RGD).

Methods and compositions for the treatment of axonal and neuronal degeneration

A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.

Semiconductor device having trench isolation for differential stress and method therefor

A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.

Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

Etch residue, resulting from a process used in forming a via, is removed using a process that does not require using a liquid chemical solvent and does not result in excessive charge build-up in the via. One step is to use a fluorocarbon and oxygen. These gases are energized by both microwave and RF. Another step is to introduce argon, in addition to the other two gases, also energized by microwave and RF. This has the effect of removing any additional residue which tends to stick on the surface above the via as well completing the removal of etch residue in the via. An additional step is simply to apply de-ionized water to remove any remaining fluorinated residue that, as a result of the preceding two steps, is highly soluable in water.

Method for removing etch residue resulting from a process for forming a via

A chromator for monitoring the end point of a plasma etching process is placed remotely from the window of a plasma etching chamber and is optically coupled to the window with a fiber optic cable bundle. The fiber optic cable bundle includes a first and a second bracket. Each bracket is specially designed to be compatible with existing chromator and plasma etching chambers. The first bracket, which attaches to the chamber, includes a plurality of slots for allowing the bracket to be axially and vertically adjusted to find the optimal optical point. Accordingly, the likelihood of the chromator properly detecting the end point is maximized. An inventive method a includes optically coupling the remotely located chromator by connecting a fiber optic cable bundle having a first bracket to the chamber, axially adjusting the bracket to find the optimal location for detecting the end point, and securing the first bracket to the chamber. The second bracket of the fiber optic cable bundle is connected to a chromator. Accordingly, light beams emitted from the chamber through the window are transmitted through the fiber optic cable bundle to the chromator for analysis.

Apparatus and method for remote endpoint detection

A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.

Device and method for etching nitride spacers formed upon an integrated circuit gate conductor

Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl,, Cl,, N,and CF,to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.

Method of fabricating sub-micron metal lines

A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.

High quality isolation structure formation

The present invention is directed to a method of fabricating very thin silicon nitride spacers on a transistor, and to a device comprising such spacers. In one illustrative embodiment, the method comprises forming a gate dielectric above a surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and forming a layer of silicon nitride above the substrate. The method further comprises performing at least one anisotropic etching process on the layer of silicon nitride using an etching recipe comprised of helium (He), sulfur hexafluoride (SF,) and hydrogen bromide (HBr). The transistor of the present invention is comprised of a gate dielectric positioned above the surface of a semiconducting substrate and a gate conductor positioned above the gate dielectric. The transistor further comprises a plurality of source/drain regions formed in the substrate adjacent the gate dielectric and a plurality of sidewall spacers comprised of silicon nitride, each of the sidewall spacers having a thickness that ranges from approximately 200-350 &angst;.

Method of fabricating ultra thin nitride spacers and device incorporating same

A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to define a channel opening for the device. A uniform nitride layer is formed over the surface of the substrate. The nitride layer is then etched to create nitride sidewall spacers. Additionally, the channel region is then etched to remove the doped portions of the active region. A gate dielectric is then formed, the gate dielectric including a nitrogen bearing oxide and a high K material. A gate conductor is then formed upon the high K material. A silicidation step is then performed. In alternative embodiments, the source/drain region is not formed and the source and drain are doped after the gate is complete. In the embodiment, the gate resides upon the active region and etching into the active region is not required. In either case, with the channel opening created to be at a lower lithographic limit, the gate conductor has a width less than the lower lithographic limit.

Method of making high performance MOSFET with channel scaling mask feature

An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a 'large tilt angle' (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor. The counter dopants fill vacancy and interstitial sites within the substrate, and thus block migration avenues through which the dopants in the junctions could otherwise pass into other areas of the substrate. The integration of the diffusion barrier layer with the counter dopant regions ensures that the dopant concentration within the junctions will be maintained.

Integration of a diffusion barrier layer and a counter dopant region to

The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a first layer of dielectric material, a plurality of source/drain regions positioned above the first layer of dielectric material, a second layer of dielectric material positioned above the first layer of dielectric material, and a layer of polysilicon positioned above the second layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above the layer of polysilicon and a gate conductor positioned above the gate dielectric.

Method of making a high performance transistor with elevated spacer

An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.

Method of fabrication for ultra thin nitride liner in silicon trench

A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.

Growing community of inventors

Austin, TX, United States of America

Thien T Nguyen