Intel Corporation

Thien Ern Ooi

David I Poisner

Eng Hun Ooi

Chai Huat Gan

Serge Bedwani

One embodiment of a technique for performing impedance compensation update operations without causing potential data corruption problems includes taking advantage of protocol idle periods, where synchronization primitives, filler data, and alignment primitives are being transmitted. For example, a serial interconnect controller may take control of the interconnect by initiating a dummy transaction. The controller can then perform an impedance compensation update operation while it is assured that no data transfers are occurring. After an appropriate settling time and after a transmission of an alignment primitive, the controller can complete the dummy transaction by issuing a no-op. This process may be re-performed periodically.

In-protocol impedance compensation control

A method and system for updating files includes transmitting a frame having status information and non-status information between a device and a host controller, storing the status information in a buffer, updating the non-status information in a non-status register, after updating the non-status information in the non-status register, determining if the frame has an error. The status register is updated if the frame includes no error.

Method and apparatus for updating task files

An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

Hardware emulation of parallel ATA drives with serial ATA interface

An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt if no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

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Penang, Malaysia

Thien Ern Ooi