Arm Limited

Other

Thibaut Elie Lanois

Guillaume Bolbenes

Houdhaifa Bouzguarrou

Yasuo Ishii

Jonatan Christoffer Lövgren

Frederic Claude Marie Piry

Luca Nassi

Florent Begon

Vincenzo Consales

Chang Joo Lee

When a predicted branch type for a given address is a first branch type corresponding to a predicated-loop instruction for triggering processing circuitry to perform a variable number of iterations of a predicated loop body, branch prediction circuitry generates a first type of branch prediction indicative of a predicted number of iterations for the predicated-loop instruction, and omits speculatively updating history information based on the predicted number of iterations. The processing circuitry is able to tolerate at least one unnecessary iteration of the predicated loop body being processed when the predicted number of iterations is too large. For a second branch type, the branch prediction circuitry generates a second type of branch prediction and, at least when a taken branch is predicted in the second type of branch prediction, speculatively updates the history information. Following detection of a misprediction of the predicted number of iterations indicated by the first type of branch prediction for the given address, it is determined whether a branch type update condition is satisfied, and if so the predicted branch type associated with the given address is switched from the first branch type to the second branch type.

Switching a predicted branch type following a misprediction of a number of loop iterations

An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence. When the confidence level for a particular multi-taken sequence satisfies a prediction confidence condition, the prediction confidence tracking circuitry allows the particular multi-taken sequence to be predicted by the prediction circuitry. The prediction circuitry causes the series of instructions and the target instruction for the particular multi-taken sequence to be identified in the fetch queue when the prediction circuitry predicts the particular multi-taken sequence and further predictions to be made starting from the target address for the particular multi-taken sequence.

Predicting upcoming control flow

An apparatus comprises a predictor to make a prediction based on a plurality of prediction tables. The plurality of prediction tables are looked up using table lookup information generated based on different lengths of input history information representing a path through program execution. The apparatus comprises circuitry to prevent a given portion of the input history information from differing with respect to a corresponding portion of the input history information used to make a preceding prediction, where the given portion is a portion which is not used to generate table lookup information for an active subset of the prediction tables.

Reduced power consumption prediction using prediction tables

Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data/instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N≥1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).

Prediction of number of iterations of a fetching process

An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.

Data storage structure

Instruction information generation circuitry generates instruction information. Instruction information storage circuitry comprises a plurality of elements having physical sub-elements configured to temporarily store units of instruction information. Allocation circuitry is configured to receive, from the instruction information generation circuitry, given instruction information. It determines a mapping of a plurality of ordered virtual sub-elements, such that each virtual sub-element maps onto a respective one of said physical sub-elements. The given instruction information is stored into the virtual sub-elements of a given element, according to the mapping, such that at least one virtual sub-element lower in said order has a higher priority than at least one virtual sub-element higher in said order. Sub-element deactivation circuitry is configured to track usage of said virtual sub-elements across the plurality of elements and adaptively deactivate virtual sub-elements.

Methods and apparatus for tracking instruction information stored in virtual sub-elements mapped to physical sub-elements of a given element

Processing circuitry performs processing operations in response to micro-operations. Front end circuitry supplies the micro-operations to be processed by the processing circuitry. Prediction circuitry generates a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry. The front end circuitry varies, based on a level of confidence in the prediction of the number of loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry.

Micro-operation supply rate variation

A data processing apparatus provides predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream and stores, with respect to each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry executes the predictable instructions in the stream using the predictions. A given correlation parameter is stored between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction to assist in generating the predictions. If the given correlation parameter is currently stored, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions. Otherwise, the prediction circuitry generates the given prediction relating to the given predictable instruction based on the set of monitored instructions.

Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction

A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

Control flow prediction

Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

Methods and apparatus for predicting instructions for execution

There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to perform data processing in response to decoded instructions and prediction circuitry to generate a prediction of a number of iterations of a fetching process. The fetching process is used to control fetching of data or instructions to be used in processing operations that are predicted to be performed by the processing circuitry. The processing circuitry is configured to tolerate performing one or more unnecessary iterations of the fetching process following an over-prediction of the number of iterations and, for at least one prediction, to determine a class of a plurality of prediction classes, each of which corresponds to a range of numbers of iterations. The prediction circuitry is also arranged to signal a predetermined number of iterations associated with the class to the processing circuitry to trigger at least the predetermined number of iterations of the fetching process.

Prediction class determination

Circuitry comprises prediction storage to store, for a given branch operation, a multi-bit data item and indicator data defining a subset of bits of the multi-bit data item, the subset being one of an ordered succession of different subsets of bits of the multi-bit data item; and prediction generator circuitry to generate a predicted branch outcome for the given branch operation in dependence upon the subset of bits defined by the indicator data and, in response to generation of the predicted branch outcome, to change the subset of bits defined by the indicator data to a next subset in the ordered succession of subsets.

Circuitry and method

An apparatus comprises a cache comprising cache entries, each cache entry storing cached information and an entry usefulness value indicative of usefulness of the cached information. Base usefulness storage circuitry stores a base usefulness value. Cache replacement control circuitry controls, based on a usefulness level determined for a given cache entry, whether the given cache entry is selected for replacement. The cache replacement control circuitry determines the usefulness level for the given cache entry based on a difference between the entry usefulness value specified by the given cache entry and the base usefulness value stored in the base usefulness storage circuitry.

Controlling cache entry replacement based on usefulness of cache entry

An apparatus and method are provided for handling incorrect branch direction predictions. The apparatus has processing circuitry for executing instructions, branch prediction circuitry for making branch direction predictions in respect of branch instructions, and fetch circuitry for fetching instructions from an instruction cache in dependence on the branch direction predictions and for forwarding the fetched instructions to the processing circuitry for execution. A cache location buffer stores cache location information for a given branch instruction for which accuracy of the branch direction predictions made by the branch prediction circuitry is below a determined threshold. The cache location information identifies where within the instruction cache one or more instructions are stored that will need to be executed in the event that a subsequent branch direction prediction made for the given branch instruction is incorrect. Control circuitry is responsive to such a subsequent branch direction prediction to obtain from the cache location buffer the cache location information and to provide the obtained cache location information to the fetch circuitry to enable the fetch circuitry to retrieve from the instruction cache the one or more instructions that are to be executed in the event that the processing circuitry does determine that the subsequent branch direction prediction was incorrect.

Apparatus and method for handling incorrect branch direction predictions

A branch predictor provides a predicted branch instruction outcome for a current block of at least one instruction. The branch predictor comprises branch prediction tables to store branch prediction entries providing branch prediction information; lookup circuitry to perform, based on indexing information associated with the current block, a table lookup in a looked up subset of the branch prediction tables; and prediction generating circuitry to generate the predicted branch instruction outcome for the current block based on the branch prediction information in the branch prediction entries looked up in the looked up subset of branch prediction tables. The looked up subset of branch prediction tables is selected based on lookup filtering information obtained for the current block. Lookups to tables other than the looked up subset are suppressed.

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Antibes, France

Thibaut Elie Lanois