Texas Instruments Corporation

Institute of Microelectronics

Other

National University of Singapore

National Research Development Corporation

Thiam Beng Lim

Cheng Qiang Cui

Tai Chong Chai

Boon Q Seow

Tadashi Saitoh

En-Tang Kang

Koon Gee Neoh

Kishore Kumar Chakravorty

Daniel Yap

Eric Neo

James Tan

Yong Chua Teo

Raymundo M Camenforte

Dennis H Sansome

Kuang Lee Tan

En Tang Kang

Soon Chye Lian

Karta W Tjandra

Ray Camenforte

Sarvotham M Bhandarkar

Junfeng Zhang

Arthur Khoon Siah Ang

Jian-Li Shi

A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.

Lead frame for an integrated circuit chip

A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

Lead frame for an integrated circuit chip (integrated circuit peripheral support)

The present invention is directed to a method for the lamination of fluoropolymers to the surfaces of metals, and especially to copper, gold, and platinum, and to printed circuit board (PCB) substrate at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of metals in the presence of a functional monomer and an adhesive such as an epoxy resin. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The laminated fluoropolymer-metal or fluoropolymer-PCB substrate interfaces exhibit T-peel strengths of no less than 8 N/cm. This invention can also be applied to substantially improve the adhesion between PCB substrates and metals.

Method for lamination of fluoropolymer to metal and printed circuit board (PCB) substrate

The present invention is directed to a method for the lamination of metals, and especially copper, to the surface of polyimides and derivatives of polyimides at temperatures substantially below the curing temperature of the imide polymers. More specifically, the invention is directed to a method for surface modification of polyimides and derivatives of polyimides by thermal graft copolymerization and interfacial polymerization with concurrent lamination of the metal of interest in the presence of an appropriate functional monomer. The process can be carried out under atmospheric conditions and either in the presence or the complete absence of an added polymerization initiator. The so laminated polyimide-metal interfaces exhibit T-peel adhesion strengths in excess of 16 N/cm. The adhesion strength also exceeds the fracture strength of polyimide films with a thickness of 75 &mgr;m.

Method for low temperature lamination of metals to polyimides

The present invention is directed to a method for the lamination of metals, and especially copper, to the surfaces of fluoropolymers at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of a metal (e.g. copper) in the presence of a functional monomer. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The so-laminated fluoropolymer-metal interfaces exhibit T-peel strengths of no less than 8 N/cm and delaminate via cohesive failure inside the fluoropolymer.

Method for low temperature lamination of metals to fluoropolymers

The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports. Alternatively, prior to encapsulation, the chip ports are positioned to sit on a mold, so that removing the mold leaves exposed the portions of the chip ports that were in contact with the mold. The mold may have an array of mold bumps or mold pockets upon which the chip ports sit. Removing the mold, exposes portions of the chip ports and leaves an array of openings in the encapsulant. Another method to form the array of openings in the encapsulant and expose portions of the chip ports uses an array of pins that are inserted in the encapsulant before it cures. The pins are inserted to contact the chip ports. Retracting the array of pins forms the array of openings in the encapsulant and exposes portions of the chip ports that were in contact with the pins.

Low cost and highly reliable chip-sized package

The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports. In another embodiment, retracting pins are positioned over the solder attach pads. The mold compound fully encapsulates the substrate, die, solder attach pads and portions of the retracting pins. Removing the retracting pins, after the encapsulation, exposes portions of the solder attach pads so that solder balls or metal bumps are attached to the exposed portions of the solder attach pads.

Method for forming a highly reliable and planar ball grid array package

Highly reliable and planar ball grid array package

The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.

IC packaging lead frame for reducing chip stress and deformation

A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a polyimide coating on its backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The polyimide coating on the backside of the integrated circuit helps to reduce package cracking arising from mounting the device to a printed circuit board by relflow solder.

Integrated circuit device and method to prevent cracking during surface

A conductive tape for a packaged semiconductor device is disclosed. The tape contains a first adhesive layer, a base film on top of the first adhesive layer, a conductive layer on top of the base film layer, and a second adhesive layer on top of the conductive layer. Metal may form the conductive layer. The tape may have slits, slots, or apertures in it so that electrical connection may be made to the conductive layer. Such a tape is useful in lead on chip integrated circuit packages to connect the semiconductor die to the lead frame and to function as a power supply bus by transferring power to the semiconductor die. Wire bonds extending through slots in the second adhesive layer form electrical connection from the lead fingers for receiving power to the conductive layer of the tape. Wire bonds extending from the bonding pads of the semiconductor die through slots the second adhesive layer form electrical connection from the semiconductor die to the conductive layer.

Lead frame without power buses for lead on chip package, and a

Integrated circuit device having a polyimide moisture barrier coating

An insulated lead frame for a semiconductor packaged device and a method of manufacturing both the insulated lead frame and the semiconductor packaged device are disclosed. The insulated lead frame has a first plurality of lead fingers and a second plurality of lead fingers. It also has the face of a power supply bus lying between the pluralities of lead fingers. An insulator covers the face of the power supply bus. An example of an insulator is a cured liquid polyimide. In a semiconductor packaged device using a lead on chip lead frame, such as a dynamic random access memory, DRAM, wire bonding that connects the power supply busses of the lead frame may first occur and the liquid insulator may afterwards be applied to the power supply busses. Alternatively, by knowing where the wire bonds will bond to the power supply busses, the liquid insulator may be applied to the power supply busses before wire bonding occurs. The bonding spots on the power supply busses are not covered with the liquid insulator. Both methods serve to reduce the possibility of shorting between the power supply busses and the crossing wire bonds that connect the lead fingers of the lead frame to the bonding pads of the integrated circuit.

Method of manufacturing insulated lead frame for integrated circuits

Conductive tape for semiconductor package, a lead frame without power

A comb insert for semiconductor packaged devices is disclosed. The comb is conductive and thus useful to function as a power supply bus in transferring power to the semiconductor die. A base, formed out of a conductive material, resides underneath the lead fingers of the semiconductor packaged device, electrically isolated from the lead fingers. The base has teeth extending from it, also formed out of the conductive material, that reside between the lead fingers of the semiconductor packaged device. Some of the teeth are electrically connected to the lead fingers for receiving external power. Some of the teeth are electrically connected to the bonding pads of the semiconductor die. Power is transferred from the lead fingers for receiving it, through the teeth electrically connected to these lead fingers, through the base, through the teeth electrically connected to the bonding pads, and to the semiconductor die. Utilizing the comb insert in a lead on chip lead frame semiconductor packaged device solves the problem of wire bond shorting to the power supply bus portions of the lead frame.

Growing community of inventors

Singapore, Singapore

Thiam Beng Lim