Beatbots, LLC

Pdf Solutions, Incorporated

Thiago G Hersan

Marek Piotr Michalowski

Gregory R Katz

Vyacheslav Rovner

Lawrence Thomas Pileggi

Matthew Moe

Veerbhan Kheterpal

Dipti Motiani

Alea C Teeters

A robot is disclosed. The robot can comprise a body and an emotion-expressing system. The emotion-expressing system can comprise a touch sensor embedded within the body, a feedback generator, and a controller in communication with the touch sensor and the feedback generator. The controller can be configured to determine the emotional state of the robot based on feedback from the touch sensor, and the feedback generator can be configured to generate feedback indicative of the emotional state.

Robot

A robot is disclosed. The robot can comprise a body comprising a curved base and a multi-directional center of mass shifter assembly positioned within the body. The multi-directional center of mass shifter assembly can comprise a weight, a first actuator drivingly coupled to the weight, and a second actuator drivingly coupled to the first actuator. Actuation of the first actuator can be configured to rotate the weight relative to a first axis, and actuation of the second actuator can be configured to rotate the weight relative to a second axis, which is transverse to the first axis. The robot can comprise an inertial measurement unit, a controller, and/or an eye movable relative to the body. The position of the eye can be adjusted by an eye actuation assembly.

A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns

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Pittsburgh, PA, United States of America

Thiago G Hersan