Freescale Semiconductor,inc.

Theresa M Keller

Dragan Zupac

Sandra J Wipf

Brian D Griesbach

Evan F Yu

Joel M Keys

Elizabeth C Glass

A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

High efficiency amplifier with reduced parasitic capacitance

A power transistor () comprises a plurality of unit cell devices (), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (), each unit cell device including base (), emitter (), and collector () portions. The base contact configuration includes (i) a first base feed () coupled to the base portion of each unit cell device via a first end of at least one base finger () associated with a corresponding unit cell device and (ii) a second base feed () coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed () coupled to the emitter portion of each unit cell device via a first end of an emitter metallization () associated with a corresponding unit cell device and (ii) a second emitter feed () coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed () coupled to the collector portion of each unit cell device.

Power transistor featuring a double-sided feed design and method of making the same

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Chandler, AZ, United States of America

Theresa M Keller