Intel Corporation

Other

Theodros Yigzaw

Mohan J Kumar

Ashok Raj

Jose Andy Vargas

Hisham Shafi

Ron Gabor

Sarathy Jayakumar

Ganapati Srinivasa

John G Holm

Geeyarpuram N Santhanakrishnan

Robert Charles Swanson

Michael Mishaeli

Julius Yuli Mandelblat

Subhankar Panda

Zeev Sperber

Shlomo Raikin

Ehud Cohen

Kuljit Singh Bains

Wei P Chen

Murugasamy K Nachimuthu

Rajat Agarwal

James B Crossland

Sergiu D Ghetie

Deep K Buch

Neeraj S Upasani

Sreenivas Mandava

Kjersten E Criss

Gaurav Porwal

Omar Avelar Suarez

Vincent J Zimmer

Raanan Sade

Raj K Ramanujan

Yen-Cheng Liu

Raghunandan Makaram

Wei Wu

Stanislav Shwartsman

Lihu Rappoport

Kai Cheng

Ishwar Agarwal

Richard Paul Mangold

Narayan Ranganathan

Jing Ling

Larisa Novakovsky

Eswaramoorthi Nallusamy

Oded Lempel

Andrew M Rudoff

Chen Koren

Camille C Raad

Cameron B McNairy

Mark Rowland

Rebecca Z Loop

William G Auld

Ronald N Story

Hsing-Min Chen

Gopikrishna Jandhyala

Anthony E Luck

Celeste M Brown

Vaibhav Singh

Tony S Baker

Chris Ackles

Rajender Kuramkote

Hugo Enrique Gonzalez Chavero

Satyaprakash Nanda

Guarav Porwal

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

Adaptive internal error scrubbing and error handling

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to provide management of a connected hardware subsystem with respect to one or more of reliability, availability and serviceability, and coordinate the management of the connected hardware subsystem with respect to one or more of reliability, availability and serviceability between the connected hardware subsystem and a host. Other embodiments are disclosed and claimed.

Cloud scale server reliability management

Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

Device, system, and method to concurrently store multiple PMON counts in a single register

In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

Hardware unit for reverse translation in a processor

In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.

System, apparatus and method for memory mirroring in a buffered memory architecture

A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

Delayed error processing

One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

System and method to increase availability in a multi-level memory configuration

In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.

Enabling error status and reporting in a machine check architecture

Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.

Hardware apparatuses and methods to check data storage devices for transient faults

Growing community of inventors

Sherwood, OR, United States of America

Theodros Yigzaw