International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Renesas Electronics Corporation

Stmicroelectronics Gmbh

Adeia Semiconductor Solutions LLC

Theodorus E Standaert

Kangguo Cheng

Veeraraghavan S Basker

Junli Wang

Tenko Yamashita

Shom Ponoth

Michael Rizzolo

Balasubramanian S Haran

Chih-Chao Yang

Benjamin David Briggs

Lawrence Alfred Clevenger

Effendi Leobandung

Daniel C Edelstein

Sivananda K Kanakasabapathy

Huiming Bu

Nicholas Anthony Lanzillo

Ali Khakifirooz

Babar Ali Khan

Kevin K Chan

Ashim Dutta

JunJun Li

Elbert Emin Huang

Christopher J Penny

Terry Allen Spooner

Stephen Edward Greco

Ruilong Xie

Bruce Bennett Doris

Chun-chen Yeh

Xiuyu Cai

Sanjay C Mehta

Andrew Herbert Simon

Ronald G Filippi

John Christopher Arnold

Robert J Gauthier, Jr

Timothy Joseph Dalton

Koichi Motoyama

Johnathan E Faltermeier

David V Horak

Ramachandra Divakaruni

Balasubramanian Pranatharthiharan

Andres Bryant

Soon-Cheon Seo

Ravikumar Ramachandran

John Anthony Fitzsimmons

Griselda Bonilla

Vamsi Krishna Paruchuri

Louis C Hsu

Roger Allan Quon

Brent A Anderson

Takashi Ando

Carl John Radens

Nicolas J Loubet

Josephine B Chang

Charles W Koburger, Iii

Terence B Hook

Takeshi Nogami

Injo Ok

Chengwen Pei

Oscar Van Der Straten

Chung-Hsun Lin

Stephen McConnell Gates

Kevin Shawn Petrarca

Souvick Mitra

Thomas N Adam

Yann Mignot

Wilfried Haensch

Marc Adam Bergendahl

Pranita Kulkarni

Muthumanickam Sankarapandian

Tom C Lee

William F Clark, Jr

Cornelius Brown Peethala

Stuart A Sieg

Henry K Utomo

Nathan P Marchack

Christopher Stephen Putnam

Alexander Reznicek

Jeffrey P Gambino

Keith Kwong Hon Wong

Son Van Nguyen

Sampath Purushothaman

Fee Li Lie

Baozhen Li

Hsueh-Chung Chen

Matthew Earl Colburn

Su Chen Fan

Laertis Economikos

Chi-Chun Liu

Hosadurga K Shobha

Xiao Hu Liu

Conal Eugene Murray

Satyanarayana Venkata Nitta

Yunpeng Yin

Min Yang

Vincent James McGahay

Donald Francis Canaperi

David Lee Rath

Dae-Gyu Park

Naftali Eliahu Lustig

Kwong Hon Wong

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

FinFET devices

A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

Modified top electrode contact for MRAM embedding in advanced logic nodes

A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Structure and method to improve FAV RIE process margin and electromigration

A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

Dielectric fill for tight pitch MRAM pillar array

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

High-density memory devices using oxide gap fill

One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Optimizating semiconductor binning by feed-forward process adjustment

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Selective recessing to form a fully aligned via

A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Pillar-based memory hardmask smoothing and stress reduction

Structure and method to improve FAV RIE process margin and Electromigration

A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.

Dual damascene with short liner

A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

Non volatile resistive memory logic device

A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.

Dielectric retention and method of forming memory pillar

A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

Embedded memory devices

A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

Embedding magneto-resistive random-access memory devices between metal levels

Growing community of inventors

Clifton Park, NY, United States of America

Theodorus E Standaert