Motorola Corporation

Theodore Zhu

Saied N Tehrani

Eugene Youjun Chen

Mark A Durlam

Jing Shi

Jon Michael Slaughter

Kelly Wayne Kyler

Gloria J Kerszykowski

Herbert Goronkin

Clarence J Tracy

A symmetric magnetic tunnel device including first and second magnetic tunnel junctions each including a pinned magnetic layer, an insulating tunnel layer and a free magnetic layer stacked in parallel juxtaposition to allow tunneling of electrons through the insulating tunnel layer between the pinned and free magnetic layers. The first and second magnetic tunnel junctions positioned in parallel juxtaposition so as to form a continuous electron path through the first and second magnetic tunnel junctions and to provide a cell signal across the first and second magnetic tunnel junctions greater than a cell signal across each of the first and second magnetic tunnel junctions individually.

Symmetric magnetic tunnel device

An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (,) having a gate (,), a drain (,) and a source (,) is integrated on a substrate (,) and coupled to a magnetic memory element (,) on the circuitry through a plug conductor (,) and a conductor line (,). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (,). Digit line (,) and bit line (,) are placed under and on top of magnetic memory element (,), respectively, and enabled to access magnetic memory element (,). These lines are enclosed by a high permeability layer (,) excluding a surface facing magnetic memory element (,), which shields and focuses a magnetic field toward magnetic memory element (,).

Magnetic random access memory and fabricating method thereof

A method of writing/reading an array of magnetoresistive cells, with each cell in the array having associated therewith a first current line that generates an easy axis field and a second orthogonal current line that generates a hard axis field when current is applied thereto. The method includes initially applying a current to the second orthogonal current lines in a first direction that generates a hard axis field to switch end domains in all cells in the array to a fixed direction, and selecting a cell in the array for write/read using a half-select technique including supplying a half-select current to the first current line associated with the selected cell to generate a half-select easy axis field and, simultaneously, supplying a half-select current in the first direction to the second current line associated with the selected cell to generate a half-select hard axis field.

Method to write/read MRAM arrays

A low aspect ratio magnetoresistive tunneling junction memory cell includes two layers of magnetoresistive material separated by electrically insulating material so as to form a magnetoresistive tunneling junction. An exchange interaction layer is sandwiched between one layer of the junction and a third layer of magnetoresistive material so as to pin the magnetic vector of one layer of the junction anti-parallel to a magnetic vector in the third layer so that magnetostatic interaction between the junction layers is canceled and the magnetic vector of the one layer is free to move in either of the two directions parallel to the polarization axis. Antiferromagnetic material is positioned adjacent the third layer so as to fix the magnetic vector in the third layer uni-directionally parallel to the polarization axis.

Low aspect ratio magnetoresistive tunneling junction

An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

A new structure of a magnetoresistive random access memory (MRAM) is presented for a high density and fast access operations. The MRAM includes two magnetic memory cells separated by an electrically conductive layer, each cell having two magnetic layers separated by a barrier layer forming a tunneling junction. Each memory cell contains one bit information as directions of magnetic vectors which are switched by an external magnetic field and sensed by a sense current flowing in the MRAM unit. The current creates a drop voltage over the MRAM unit, which indicates four different values according to the states stored in MRAM unit.

Magnetic memory unit having four states and operating method thereof

A non-volatile magneto-resistive memory positioned on a semiconductor substrate is shielded from stray magnetic fields by a passivation layer partially or completely surrounding the non-volatile magneto-resistive memory. The passivation layer includes non-conductive ferrite materials, such as Mn--Zn-Ferrite, Ni--Zn-Ferrite, MnFeO, CuFeO, FeO, or NiFeO, for shielding the non-volatile magneto-resistive memory from stray magnetic fields. The non-conductive ferrite materials may also be in the form of a layer which focuses internally generated magnetic fields on the non-volatile magneto-resistive memory to reduce power requirements.

Stray magnetic shielding for a non-volatile MRAM

A new magnetic random access memory (MRAM) unit (30) is provided suitable for fabricating a MRAM device (20). The MRAM cell includes a magnetic storage element (32) and a current control element (33), for example, a diode, connected to the magnetic storage element in series to control a current in the magnetic storage element. The magnetic storage element has two magnetoresistive layers (36,38) separated by a non-magnetic layer (37), for example, aluminum oxide (Al.sub.2 O.sub.3). The diode allows a current to flow in only an MRAM cell activated by a column line and a row line.

Multi-layer magnetic random access memory and method for fabricating

A magnetic device (40) having multi-layer (41-45) with insulating layer (45) and conductive layer (42). The conductive layer (42) is positioned between a first magnetic layer (41) and a third magnetic layer (44). The insulating layer (45) is positioned between a second magnetic layer (43) and the third magnetic layer (44), and which forms a tunnel junction between the second and third layers. Magnetic vectors in the first magnetic layer (41) magnetically couple with ones in the second magnetic layer (43) so that the magnetic coupling loop formed around the third magnetic layer (44) allows magnetic vectors in the third magnetic layer (44) to be switchable in a low magnetic field. Consequently, total power consumption of the magnetic device (60) decreases.

Magnetic device having multi-layer with insulating and conductive layers

A multi-layer magnetic memory cell is provided, with magnetic vectors aligned along a length of the cell. To align the magnetic end vectors, an ellipsoidal shape is formed at the ends of the memory cell. Magnetic vectors aligned along the length prevent from forming high fields and magnetic poles at the discontinuity or ends of the layers. The memory cell with the ellipsoidal shape shows a constant magnetic resistance of the magnetic cell when a magnetic field is applied to the cell and attains a reduction of power consumption for the magnetic cell.

Growing community of inventors

Chandler, AZ, United States of America

Theodore Zhu