Texas Instruments Corporation

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Sun Microsystems, Inc.

Texas Instruments Incorproated

Theodore Warren Houston

Xiaowei Deng

Patrick W Bosshart

Andrew Marshall

Michael Patrick Clinton

Anand Seshadri

Henry M Darley

Hugh Thomas Mair

Terence G Blake

Kayvan Sadra

Amitava Chatterjee

Thomas J Aton

Bryan David Sheffield

Keith Alan Joyner

Wah Kit Loh

Scott William Jessen

Douglas J Matzke

Ching-Hao Shaw

Vibhu Kalyan

Vinod J Menezes

Shyh-Horng Yang

Lakshmikantha V Holla

Robert R Garcia

David Barry Scott

Richard A Chapman

Al F Tasch, Jr

Donald George Mikan, Jr

James Bernard Kruger

Yin Hu

Robert Soper

Luan A Dang

Chauncey L Everett

Horng S Fu

James B Burr

Zhiqiang (Jeff) Wu

Howard L Tigelaar

Sudhir Kumar Madan

Somnath S Nag

Robert L Pitts

Jarvis Benjamin Jacobs

Jeffrey A McKee

Shaoping Tang

Ih-Chin Chen

Gordon P Pollack

Song Zhao

Makarand Ramkrishna Kulkarni

Russell Carlton McMullan

Puneet Kohli

James D Gallia

Tito Gelsomini

Keerthinarayan P Heragu

Srinivasa Raghavan Sridhara

Sreenath Unnikrishnan

Peter S McAnally

Guohong Zhang

Hsindao E Lu

Iqbal Ali

Larry R Hite

Ping Yang

Sudha Thiruvengadam

Sreedhar Natarajan

Han T Yuan

Donald Mikan

James (Hsu-Hsuan) Lan

James H Liou

Ching-Heo Shaw

Robert A Bell

Agerico L Esquirel

An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

SRAM cell with T-shaped contact

An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell.

SRAM cell having an n-well bias

An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.

Integrated circuit with low power SRAM

A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the array supply voltage and an NFET with its source connected to ground and its drain connected to the word line. The NFET is inactivated before the PFETs are activated. One of the PFETs is activated before the other PFET is activated so as to control the slew rate of the word line and improve the static noise margin of the at least one bit cell.

Read assist for an SRAM using a word line suppression circuit

A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.

Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving the array supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a first switch coupled in series and a second switch. The switches are responsive to a control signal. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Read assist circuit for an SRAM, including a word line suppression circuit

An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.

SRAM cell parameter optimization

An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

SRAM cell with different crystal orientation than associated logic

An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line.

8T SRAM cell with one word line

A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a driver in an addressed SRAM cell. A process of performing an SRAM double sided write operation including applying a positive bias increment to an isolated p-well containing a passgate connected to a low data line in an addressed SRAM cell. A process of performing an SRAM double sided read operation including applying a negative bias increment to an isolated p-well containing a bit driver and applying a negative bias increment to an isolated p-well containing a bit-bar driver in an addressed SRAM cell.

SRAM cell having a p-well bias

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Read assist circuit for an SRAM

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Richardson, TX, United States of America

Theodore Warren Houston