Siemens Corporation

Theodore W Wagner

Morris L Minch

Deepak R Muzumdar

Rolf E Schneider

Donald F Gray

William A Levine

Sam Liang

Gerry Suarez

Samuel Liang

Ramesh M Vyas

A transformerless hybrid circuit arrangement for a subscriber line interface circuit of a telecommunications exchange is disclosed. A preferred embodiment of the hybrid arrangement comprises a first and a second operational amplifier plus a differential amplifier connected together in the following manner: The non-inverting input of the first operational amplifier is connected to a first reference voltage and the output of this amplifier is connected (1) via a first resistor to one wire of the two-wire subscriber line, and (2) via a third resistor to the inverting input of the amplifier. The non-inverting input of the second operational amplifier is connected to a second reference voltage and to the receiving branch of the four-wire line of the telecommunications exchange. The output of this second operational amplifier is connected via a second resistor to the other wire of the two-wire subscriber line, via a fourth resistor to the inverting input thereof and via a fifth resistor to the inverting input of the first operational amplifier. Each of the two inputs of the differential amplifier are connected, via respective resistors, to one wire of the two-wire subscriber line and to the output of that operational amplifier which is connected to the other wire of the two-wire subscriber line. The output of the differential amplifier is connected to the transmitting branch of the four-wire line of the exchange.

Apparatus for transmitting and/or receiving balanced signals on a

A transceiver for use with a digital telephone apparatus adapted to be connected for duplex communication to a telephone speech transmission line includes a receiving unit and a transmitting unit. The receiving unit processes an incoming serial ternary level signal stream composed of alternate mark inverted (AMI) encoded pulses and received from the transmission line. A compensation filter compensates distortions of the transmitted signals. A full wave rectifier circuit generates unipolar output signals. A pulse detection circuit derives rectangular pulses from the unipolar output signals. A phase-locked loop (PLL) circuit reconstructs a clock pulse train from the rectangular pulses. The transmitting unit receives an outgoing serial data stream from the telephone apparatus and internal clock pulses from that PLL circuit and includes means for converting the pulses of the outgoing data stream into AMI encoded signals.

Transceiver unit for a telecommunication system

A ring trip detector for a subscriber line interface circuit which couples a two-wire subscriber line with the transmitting and receiving branches, respectively, of a four-wire line in a telecommunication exchange. The subscriber line interface circuit includes a two-to-four wire hybrid circuit having an off-hook detector; a ring generator for producing an AC ring voltage of given frequency for ringing a subscriber set connected to the subscriber line; and a ring relay for selectively connecting the hybrid circuit to the subscriber line when in a first position and connecting the ring generator to the subscriber line when in a second position. The ring trip detector includes a first circuit, which receives a first signal representing the off-hook condition of the subscriber set and a second signal that is synchronized with zero crossings of said ring voltage, for producing a synchronized off-hook signal at the next, subsequent zero crossing of the ring voltage after said first signal indicates the presence of the off-hook condition; and a second circuit, which receives the synchronized off-hook signal, for switching the relay to its first position.

Ring trip detector for a subscriber line interface circuit

Digital telephone apparatus suitable for use as a subscriber station as well as for an attendant console. The telephone apparatus is connectable for full duplex communication with a four wire telephone transmission line. The telephone apparatus is capable of transmitting PCM speech data and/or digital data from a digital data interface to a peripheral data system. The telephone apparatus comprises an internal data bus to which are connected a digital transceiver, a sync/signalling generator, a serial frame synchronizer and at least one codec/PCM filter. The transceiver transmits and receives digital data to and from the telephone transmission line. The sync/signalling generator repeatedly supplies an 8 bit first data word to the internal data bus containing a binary synchronizing code and a signalling code. Simultaneously, the serial frame synchronizer repeatedly receives from the data bus and decodes an 8 bit first data word containing a synchronizing code and a signalling code. The codec/PCM filter repeatedly receives from and transmits to said internal data bus 8 bit PCM voice samples as additional data words immediately following the first data word. A microcomputer, including a number of input/output devices, receives successive signalling codes from the serial frame synchronizer and repeatedly transmits signalling codes to the sync/signalling generator for communicating with the telephone exchange to which the apparatus is connected.

Digital telephone apparatus

A modular telephone keyset instrument is arranged within a rectangular casing having indentations in the top for receiving a telephone handset. Electrical (electronic) circuits are provided on a mother PC board, a daughter PC board and a key switch PC board, stacked within the housing from bottom to top, respectively. The daughter and keyset PC boards are connected to the mother PC board by ribbon cables. A hook switch, mounted on and attached to the daughter PC board extends through one of the indentations in the top to sense whether the telephone handset is placed in the indentations.

Modular telephone keyset structure

A synchronizing circuit for use with a digital communication system is disclosed. A serial data stream is arranged in frames composed of at least two data words containing a synchronization signalling code and binary coded information, respectively. For detecting the alignment of consecutive frames the synchronizing circuit includes a serial/parallel converter and a synchronizing detector logic network for generating two control signals indicating the presence of the synchronization code in form of a normal synchronizing bit pattern or an inverted synchronizing bit pattern respectively. An AND-gate logically links the first control signal delayed by one pulse frame to the undelayed second control signal and generates a synchronizing signal. A time slot generator produces enabling signals by means of counting subsequent system clock pulses under control of this synchronizing signal such that during receiving of different data words of a frame a respective one of the enabling signals is present.

Growing community of inventors

West Palm Beach, FL, United States of America

Theodore W Wagner