Micron Technology Incorporated

Micron Telecommunications, Inc.

Theodore T Pekny

Victor Y Tsai

Stephen J Gualandri

Violante Moschiano

Michele Piccardi

Peter Sean Feeley

Vipul Patel

Steve Gualandri

Luca De Santis

Michele Incarnati

Jae-Kwan Park

William Henry Radke

Vishal Sarin

Tommaso Vali

Giovanni Naso

Pin-Chou Chiang

Qiang Tang

Samuel A Shapero

Aaron S Yip

Brady L Keays

Wanmo Wong

Jeff Yu

Taehyun Kim

Arvind Muralidharan

Vivek Venkata Kalluru

James I Esteves

Pinchou Chiang

Jun Xu

Ramin Ghodsi

Kirubakaran Periyannan

Pin-Chuo Chiang

Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

Charge loss compensation during read operations in a memory device

Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Block or page lock features in serial interface memory

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Apparatuses including multiple read modes and methods for same

Arrays of memory cells including an isolation region between first and second access lines, a first memory cell having a control gate in contact with the first access line and a charge storage node having a curved cross-section having a first end in contact with a first portion of the isolation region on a first side of the isolation region and a second end in contact with a second portion of the isolation region on the isolation region's first side, and a second memory cell having a control gate in contact with the second access line and a charge storage node having a curved cross-section having a first end in contact with the first portion of the isolation region on a second side of the isolation region and a second end in contact with the second portion of the isolation region on the isolation region's first side.

Arrays of memory cells including pairs of memory cells having respective charge storage nodes between respective access lines

Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

Systems and methods involving hardware-based reset of unresponsive memory devices

A system and a memory device including a driver circuit, to perform first operations including driving a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The system and memory device including the RC sensor circuit, coupled to the driver circuit, to perform second operations including determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit. The ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Extracting the resistor-capacitor time constant of an electronic circuit line

A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Defect detection during program verify in a memory sub-system

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Apparatuses and methods for concurrently accessing different memory planes of a memory

A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

Charge loss detection using a multiple sampling scheme

A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to detect an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to manage execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.

Noise reduction during parallel plane access in a multi-plane memory device

A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.

Independent parallel plane access in a multi-plane memory device

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

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Sunnyvale, CA, United States of America

Theodore T Pekny