Texas Instruments Corporation

Other

Agilent Technologies, Inc.

University of Florida Research Foundation Inc

Advanced Technology Materials, Inc.

Agilent Technologies Texas Instruments Incorporated

Theodore Sidney Moise

Scott Robert Summerfelt

Luigi Colombo

Francis Gabriel Celii

Sanjeev Aggarwal

Stephen Roy Gilbert

Guoqiang Xing

Kezhakkedath Ramunni Udayakumar

K R Udayakumar

Mark R Visokay

Justin F Gaynor

Kelly Jay Taylor

Lindsey H Hall

Glen D Wilk

Robert Kraft

Alan J Katz

Yung-Chung Kao

Martin G Albrecht

J Scott Martin

Henry Litzmann Edwards

Gary A Frazier

Hugh Pryor McAdams

Marie Denison

Peter C Van Buskirk

Shawming Ma

Abbas Ali

Yaw S Obeng

John Anthony Rodriguez

Jun Amano

Jarrod Eliason

Gregory Boyd Shinn

Toshikazu Nishida

Michael W Russell

Daniel J Vestyck

Tomoyuki Sakoda

Mark A Kressley

Chiu Chi

Charles D E Lakeman

Stacey A Yamanaka

Bill Kraus

Sarah Hartwig

Yung Shan Chang

Antonio Guillermo Acosta

Rahim Kavari

Jeff L Large

Sirisha Kuchimanchi

Tomojuki Sakoda

Alvin L S Loke

Laura Wills-Mirkarimi

Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.

Enhancement of properties of thin film ferroelectric materials

A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.

MEMS device fabricated with integrated circuit

A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Method for leakage reduction in fabrication of high-density FRAM arrays

A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60&#xb0; C.

Ferroelectric capacitor manufacturing process

One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.

Method of forming PZT ferroelectric capacitors for integrated circuits

A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Method for cleaning post-etch noble metal residues

Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same

A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Integrated circuit and method

Methods () are provided for fabricating a ferroelectric capacitor structure including methods () for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching () portions of an upper electrode, etching () ferroelectric material, and etching () a lower electrode to define a patterned ferroelectric capacitor structure, and etching () a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing () the patterned ferroelectric capacitor structure using a first ashing process, performing () a wet clean process after the first ashing process, and ashing () the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Ferroelectric capacitor stack etch cleaning methods

Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C) from hydrogen diffusion in semiconductor devices (), wherein nitrided aluminum oxide (N&#x2014;AlOx) is formed over a ferroelectric capacitor (C), and one or more silicon nitride layers () are formed over the nitrided aluminum oxide (N&#x2014;AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N&#x2014;AlOx) is formed over the ferroelectric capacitors (C), with two or more silicon nitride layers () formed over the aluminum oxide (AlOx, N&#x2014;AlOx), wherein the second silicon nitride layer () comprises a low silicon-hydrogen SiN material.

Ferroelectric capacitor hydrogen barriers and methods for fabricating the same

Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components

Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device

Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same

Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C) from hydrogen diffusion in semiconductor devices (), wherein nitrided aluminum oxide (N&#x2014;AlO) is formed over a ferroelectric capacitor (C), and one or more silicon nitride layers () are formed over the nitrided aluminum oxide (N&#x2014;AlO). Hydrogen barriers are also provided in which an aluminum oxide (AlO, N&#x2014;AlO) is formed over the ferroelectric capacitors (C), with two or more silicon nitride layers () formed over the aluminum oxide (AlO, N&#x2014;AlO), wherein the second silicon nitride layer () comprises a low silicon-hydrogen SiN material.

Growing community of inventors

Dallas, TX, United States of America

Theodore Sidney Moise