Dcg Systems Gmbh

Credence Systems Corporation

Nxp Usa, Inc.

Schlumberger Technologies, Inc.

Carl Zeiss Smt Gmbh

Fei Comapny

Nptest, Inc.

Theodore R Lundquist

Chun-Cheng Tsao

Erwan Le Roy

William B Thompson

Mark Alan Thompson

Ketan Shah

Romain Desplats

Philippe Perdu

Keith Serrels

Kent Erington

Lokesh Johri

Daniel Joseph Bodoh

Vladimir V Makarov

Madhumita Sengupta

Rajesh Kumar Jain

Saurabh Gupta

Martin Betz

Baohua Niu

Kenneth R Wilsher

Patricia Le Coupanec

James Henry Brown

Eugene A Delenia

Christian Boit

Michael A Cecere

Euan Ramsay

Catherine Kardach

Xavier Larduinat

Tamal Basu

Tamayasu Anayama

Jagadish Narayana Gade

Uwe Jürgen Kerst

Stephan Schoemann

Peter Sadewater

Mamta Slnha

Qinsong Steve Wang

Tzong Tsong Miau

Christopher Shaw

Mamta Sinha

A method for analyzing an integrated circuit includes: applying an electric test pattern to the IC; delivering a stream of primary electrons to a back side of the IC on an active region to a transistor of interest, the active region including active structures such as transistors of the IC; detecting light resulting from cathodoluminescence initiated by secondary electrons in the IC; and analyzing the detected light regarding a correlation with the electric test pattern applied to the IC. A system for analyzing an IC is provided.

Method and system for testing an integrated circuit

Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Synchronized pulsed LADA for the simultaneous acquisition of timing diagrams and laser-induced upsets

Systems, methods, and computer readable media to improve the operation of thermographic imaging systems are described. Techniques are disclosed for generating thermograms using single low-noise photon detectors. More particularly, an array of single low-noise photon detectors operating in the Geiger mode may be used to accurately identify the time delay between the application of a periodic power stimulus to a device under test and the generation of photons resulting from that stimulus. In one embodiment an array of single photon detectors may be used to time-tag each detected photon. Thereafter, a high-speed counting circuit can correlate the detected photons to the applied stimulus. When operating at the frequencies possible in the Geiger mode, such measurements permit a higher degree of spatial resolution (e.g., in the x, y and z axes) of thermal hot-spots within the device under test than prior art approaches.

High frequency lock-in thermography using single photon detectors

An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

Apparatus and method for optical interference fringe based integrated circuit processing

Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.

FIB milling of copper over organic dielectrics

An analysis system has a charged particle beam instrument and a scanning probe microscope operably coupled with the charged particle beam instrument. A stage defines an aperture, the stage is adapted to support the sample over the aperture and finely move the sample at least along an X and Y axis, the aperture further situated in an operable area of the charged particle beam. The charged particle beam is used to mill the sample, while the scanning probe microscope is used to measure elements exposed by the milling.

Methods and systems of performing device failure analysis, electrical characterization and physical characterization

An improved method, apparatus, and control/guiding software for localizing, characterizing, and correcting defects in integrated circuits, particularly open or resistive contact/via defects and metal bridging defects, using FIB technology. An apparatus for identifying an abnormal discontinuity in a contact/via in an integrated circuit comprising a focused ion beam system to scan the ion beam over the contact/via to do remove or deposit via material, a detector to collect a secondary particle signal from the contact/via material that gets removed, a sub-system for storing the secondary particle signal from the contact/via in time as well as x-y scan position, a sub-system for correlating secondary particle signals and identifying discontinuities in the correlated secondary particle signals, a sub-system for optimizing the display of the abnormal discontinuity; and a computer to implement software aspects of the system.

FIB based open via analysis and repair

An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a front-end environment with access to integrated circuit computer aided design tools providing logic level and layout level information concerning the integrated circuit. The front-end environment incorporates circuit operation optimization methods to identify optimal locations for a circuit operation. A back-end environment, such as a charged particle tool computing platform, is adapted to receive one or more files, which may include a truncated layout file with circuit operation location information, for use in further defining a circuit operation and/or performing the circuit operation.

Apparatus and method for circuit operation definition

Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Apparatus and method of forming silicide in a localized manner

A plurality of images, including a first image and a second image having a higher resolution than the first image, are aligned by generating an oversampled cross correlation image that corresponds to relative displacements of the first and second images, and, based on the oversampled cross correlation image, determining an offset value that corresponds to a misalignment of the first and second images. The first and second images are aligned to a precision greater than the resolution of the first image, based on the determined offset value. Enhanced results are achieved by performing another iteration of generating an oversampled cross correlation image and determining an offset value for the first and second images. Generating the oversampled cross correlation image may involve generating a cross correlation image that corresponds to relative displacements of the first and second images, and oversampling the cross correlation image to generate the oversampled cross correlation image.

Sub-resolution alignment of images

A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.

Apparatus and method for detecting photon emissions from transistors

A charged particle guide adapted to be coupled with a charged particle detector, such as a secondary electron detector. The charged particle guide, in one example, comprising two wires extending from the charged particle detector toward a source of charged particles, such as secondary electrons emitted from an IC upon application of a focused ion beam. Upon application of a bias voltage, the charged particle guide introduces a collecting electric field that attracts charged particles and directs the charged particles to the charged particles detector.

Charged particle guide

The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.

Method and system for integrated circuit backside navigation

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Dublin, CA, United States of America

Theodore R Lundquist