International Business Machines Corporation

Theodore M Redman

Endre P Thoma

Robert E Busch

Wayne Frederick Ellis

William Paul Hovis

Scott C Lewis

Frederick J Aichelmann, Jr

Edward Butler

Bruce E Bachman

James A Yankosky

James Edward Rock

Donald Lawrence Wilder

A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages. The memory chip also includes a gating structure for gating the respective groups of stages to the N data unit parallel output interface, the gating structure including at least a first gate circuit for gating in parallel the data units held in the first group of stages to the N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in the second group of stages to the N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.

Fast access memory structure

A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

Signal margin testing system for dynamic RAM

A method and device for setting at least three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

Multiple mode-set for IC chip

A memory device which includes several partially defective memory chips and a control circuit for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled.

Memory module utilizing partially defective memory chips

A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

Growing community of inventors

Milton, VT, United States of America

Theodore M Redman