International Business Machines Corporation

Theodore Joseph Bohizic

Reid T Copeland

Mark H Decker

Marcel Mitran

Ali Ijaz Sheikh

Ali Y Duale

Viktor Sandor Gyuris

Dennis W Wittig

Richard T Brandle

Shakti Kapoor

Stephen R Valley

Shailesh Ratilal Gami

Walid M Kobrosly

Ying-Yeung Li

Rahul Chandrakar

Paul M Gioquindo

Ping T Chan

Viktor Gyuris

Kirk A Stewart

Gary R Morrill

Michael S Cirulli

George A Darling

Vincent L Ip

Mark Decker

Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.

Page mapped spatially aware emulation of computer instruction set

A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.

Just in time compiler in spatially aware emulation of a guest computer instruction set

Optimizations are provided for processing environments. Selected memory objects are tagged with unique identifiers by an operating system of the environment, and those identifiers are used to manage processing within the environment. By detecting by a processing platform of the environment that a memory object has been tagged with a unique identifier, certain tasks may be bypassed and/or memory objects may be reused, even if located at a different location.

Employing identifiers provided by an operating system of a processing environment to optimize the processing environment

A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.

Self initialized host cell spatially aware emulation of a computer instruction set

A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator.

Executing atomic store disjoint instructions

Page mapped spatially aware emulation of a computer instruction set

Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.

Reusing invalidated traces in a system emulator

A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.

Host cell spatially aware emulation of a guest wild branch

An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.

Facilitating input/output processing of one or more guest processing systems

A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Storage medium for estimating and improving test case generation

System for estimating and improving test case generation

Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.

Providing memory consistency in an emulated processing environment

Instruction execution is facilitated by employing a buffer to handle instructions having special circumstances. When such an instruction is to be executed, a pointer of the instruction is directed to the buffer. The instruction is executed from the buffer and then the pointer is recovered to point to a location other than the buffer.

Employing a buffer to facilitate instruction execution

A method, system, and computer program product for generating terminating, pseudo-random test instruction streams, including forward and backward branching instructions. A first instruction stream is generated, including at least one backward branching instruction and at least one forward branching instruction. Each backward branching instruction is preceded by at least one forward branching instruction, which is used to guarantee termination of the loop formed by the backward branching instruction. Backward branching targets are resolved when the backward branching instruction is inserted into the first instruction stream. Forward branching targets remain unresolved in the first instruction stream. A set of potential branch targets is determined for each forward branching instruction. For each forward branching instruction, a branch target is randomly selected from the set of potential branch targets for that forward branching instruction. The final terminating instruction stream consists of the first stream, with all forward branch targets resolved.

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Hyde Park, NY, United States of America

Theodore Joseph Bohizic