International Business Machines Corporation

Theodore James Yoder

Andrew W Cross

Guanyu Zhu

Christopher Chamberland

Jay Michael Gambetta

Jared Barney Hertzberg

Youngseok Kim

Antonio Corcoles-Gonzalez

Maika Takita

Neereja Sundaresan

Tomas Raphael Jochym-O'Connor

Edward Hong Chen

Riddhi Swaroop Gupta

Benjamin James Brown

Techniques regarding quantum error correction are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a maximum-likelihood decoder component that executes a maximum-likelihood decoding algorithm to determine an error correction based on a decoding hypergraph that characterizes error-sensitive events associated with a quantum error-correcting code executed on a quantum circuit.

Maximum-likelihood decoding of quantum codes

According to an embodiment of the present invention, a method, system, and computer program product for preparing a CZ state for use in magic state distillation. The embodiment may include initializing a code state across data qubits. The embodiment may include measuring a CZ operator of the codes state on at least one ancilla qubit proximal to the data qubits. The embodiment may include performing additional quantum operations with the CZ state based on the measurement of the at least one ancilla qubit.

Preparation of a CZ state for quantum computation

A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

Quantum code for reduced frequency collisions in qubit lattices

Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.

Calibrated decoders for implementations of quantum codes

A method of error correction for a quantum computer includes identifying each of a plurality of physical qubits arranged in a lattice pattern over a surface in a quantum processor of the quantum computer as a one of a data qubit, an ancilla qubit or a flag qubit to define a plurality of data qubits, ancilla qubits and flag qubits. Each pair of interacting data qubits interact with a flag qubit and adjacent flag qubits both interact with a common ancilla qubit. The method further includes performing measurements of weight-four stabilizers, weight-two stabilizers, or both of a surface code formed using at least a sub-plurality of the plurality of physical qubits, or performing measurements of weight-four Bacon-Shor type gauge operators; and correcting fault-tolerantly quantum errors in one or more of the at least sub-plurality of physical qubits based on a measurement from at least one flag qubit.

Using flag qubits for fault-tolerant implementations of topological codes with reduced frequency collisions

Techniques regarding encoding a quantum circuit to a trivalent lattice scheme to identify flag qubit outcomes are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a graph component that can encode a quantum circuit to a trivalent lattice that maps an ancilla qubit to a plurality of data qubits via a plurality of flag qubits based on a connectivity scheme of the quantum circuit.

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White Plains, NY, United States of America

Theodore James Yoder