Unisys Corporation

Theodore J Skapinetz

Jay L Gerbehy

Kenneth J Burkhardt, Jr

Patrice M Bremond-Gregoire

Patrice M Bermond-Gregoire

Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interrupt signal represented by the data. The stages of the register are connected to the associated interrupt input of the other processor.

Intercomputer communication control apparatus and method

Interprocessor message communication synchronization apparatus and method for a plurality of processors connected to a system bus where one processor desiring to send a control signal to another processor, broadcasts an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the control signal to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate control signal represented by the data. The stages of the register are connected to the associated control signal inputs of the other processor. In this manner the one processor may transmit a message synchronizing interrupt to the other processor.

Growing community of inventors

Bloomsburg, NJ, United States of America

Theodore J Skapinetz