Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Avago Technologies General IP (singapore) Pte. Ltd.

Theodore G Rossin

Alan S Krech, Jr

Jon L Ashburn

Edmundo Rojas

Glenn W Strunk

S Paul Tucker

Ted Scott Rakel

Michael S McGrath

Byron Alan Alcorn

Russ William Herrell

Larry S Metz

Ronnie E Owens

Courtney D Goeltzenleuchter

James M Dewey

Bradley W Cain

Kendall F Tidwell

Eric C Nelson

A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.

Method and apparatus for calibrating delay lines

The pseudo-linear frame buffer mapping system and method facilitates the clearing of the frame buffer memory of a graphics display system by subdividing the region of the frame buffer which is to be cleared into a plurality of sub-regions and by initiating the clear command concurrently to each of the plurality of sub-regions.

Pseudo-linear frame buffer mapping system and method

A rasterizer implementing a single edge stepping interpolator to interpolate both diffuse and specular lighting components across an edge of the primitive, and/or a single span stepping interpolator to interpolate both diffuse and specular lighting components across the spans of the primitive. When the edge or span being interpolated includes a non-negligible specular lighting component, the diffuse and specular lighting components are separately and successively rasterized. Otherwise, only the diffuse lighting component is interpolated over the edge or span.

Efficient rasterization of specular lighting in a computer graphics system

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

ROM-based control unit in a geometry accelerator for a computer graphics system

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.

Centralized branch intelligence system and method for a geometry accelerator

A system and method for performing view clipping and model clipping of graphics primitives in a geometry accelerator of a computer graphics system. The method includes performing view clipping and model clipping of the graphics primitives in homogeneous window coordinates. The geometry accelerator includes a transform machine, a light machine, a clipping machine, and a plane equation machine. The transform machine receives vertex data defining a graphics primitive, in object coordinates, and transforms the vertex data into homogeneous window coordinates. The light machine receives the transformed vertex data from the transform machine and enhances the transformed vertex data by simulating lighting conditions of the graphics primitive. The light machine provides light enhanced transformed vertex data to the clipping machine. The clipping machine receives the light enhanced vertex data from the light machine and determines intersections of edges of the graphics primitive with view clipping planes and with any user specified model clipping planes. The resulting clipped vertex data from the clipping machine is provided to the plane equation machine. The plane equation machine calculates plane equations defining geometries formed by the clipped vertex data and provides the calculated plane equations to the computer graphics system for display.

Post transformation clipping in a geometry accelerator

ROM-based control units in a geometry accelerator for a computer

The present invention provides a method and apparatus for processing primitives in a computer graphics display system. The present invention comprises a geometry accelerator for processing polygons to provide two-sided lighting for front and back facing polygons. The geometry accelerator comprises a lighting machine and a memory device in communication with the lighting machine. The geometry accelerator receives command data, vertex data, and parameter data from a central processing unit (CPU) of a computer graphics display system. The vertex data comprises polygon vertex color data, vertex coordinate data and vertex normal data. The parameter data comprises front and back material parameters. The command data comprises information relating to the type of primitive to be processed by the lighting machine. The geometry accelerator looks at the command data to determine whether the polygon is a front or back facing polygon and informs the lighting machine as to whether the polygon is a front or back facing polygon. The lighting machine will then fetch the correct set of material parameters and use them to calculate lighting.

Method and apparatus for processing primitives in a computer graphics

A system and method for reducing an amount of memory that is needed to perform view clipping and model clipping of an input primitive in a geometry accelerator of a computer graphics system. The method includes view clipping the input graphics primitive with each view clipping boundary to determine a view-clipped geometry, storing view-clipped vertex data defining the view clipped geometry in memory, model clipping a view-clipped triangle forming the view-clipped geometry with each user defined model clipping plane to determine a model-clipped geometry, and storing model-clipped vertex data defining the model-clipped geometry in the memory in the memory locations previously occupied by said view-clipped vertex data. The method is repeated until each view-clipped triangle forming the view-clipped geometry has been model-clipped.

Multi-pass clipping in a geometry accelerator

Apparatus for performing floating point divide operations includes a divider and a comparator. The divider performs a floating point divide operation on a floating point numerator and a floating point denominator. The comparator performs a comparison of the floating point denominator, except for a sign bit of the floating point denominator, with a floating point value of 0.0. A logic element, responsive to a control signal indicative of the floating point divide operation, provides to the comparator equal sign bits associated with the floating point denominator and the floating point value of 0.0. A result of the comparison indicates a divide by zero operation and is independent of the sign of the floating point denominator. The result of the comparison is used to determine a course of action before the divide operation is completed.

Methods and apparatus for fast check of floating point zero or negative

Extra hardware to compute the fifth vertex of a bow-tie quadrilateral is avoided by using the clipping system to do the calculations. This is accomplished by inspecting quadrilaterals (as they are projected onto the viewing plane) to see if they contain pairs of self-intersecting sides. Those that do are further classified as to type and subtype, depending respectively upon how the vertex numbering scheme identifies the intersecting non-adjacent sides and upon which of X and Y is the major axis. The hardware normally associated with a clipper can be 'borrowed' and used in a non-clipping fashion to find the X coordinate for a YZ work plane (or the Y coordinate for an XZ work plane) that is associated with the fifth vertex (V.sub.4) created by the self-intersection. Once this is done the hardware of the clipper can be further borrowed to actually intersect (i.e., clip) one of the self-intersecting sides with that work plane, which produces a complete description of all the pixel coordinates for V.sub.4. Once V.sub.4 is known the bow-tie is divided into two triangles, each containing two adjacent vertices not found in the other triangle and each also containing V4 as a common vertex.

Clipper assisted decomposition of bow-tie quadrilaterals

A triangle primitive to be clipped against a viewing volume is clipped six times; once against each plane of the viewing volume. During each such clipping operation phantom vertices are discovered and the hardware vertex locations they occupy are made available for re-use. The discovery of phantom vertices is accomplished by three rules. Rule #1 is: If a previous vertex in the vertex list is outside the clip limits and is not the starting vertex, then that previous vertex's location in the vertex list can be re-used. Rule #2 is: If the current vertex in the vertex list is outside the clip limits and is the starting vertex, then the location in the vertex list containing the data for that starting vertex can be re-used to contain the intersection of that last edge and the clipping plane. Rule #3 is: If the current vertex in the vertex list is outside the clip limits and there has already been an intersection between the clipping plane and another edge, then the locations in the vertex list containing the data for vertices from that current vertex and beyond can be re-used to contain any new vertices. These rules are implemented by various state machines that also control the clipper.

Clipper re-uses storage locations allocated for verticles

A hardware graphics accelerator accepts lists of polygon vertices from an application environment running application and systems graphics software. After a polygon is rotated and translated as needed, it is checked for trivial accept/reject against the clip limits of the viewing volume, but is not otherwise clipped. Polygons that are not rejected are decomposed into triangles before any other operations on them are performed. After decomposition the triangles are illuminated by light sources, if desired and then clipped by a triangle clipper, rasterized, and the results sent to a frame buffer for display. The triangle clipper incorporates trivial accept/reject operation, and is capable of operating on non-planar quadrilaterals. It avoids ugly artifacts during certain clip operations when the diagonal used to decompose a quadrilateral into triangles intersects a clip plane not parallel to the viewing axis. It does this by replacing the point of intersection along that diagonal that the clipper would ordinarily find with a point that is the projection of that diagonal onto a line between two adjacent points of intersection of the actual edges of the quadrilateral with the clip plane.

Method and apparatus for clipping non-planar polygons

A control logic unit outputs a group of encoded control signals that have less redundancy than the FPU signals needed to control a floating point processor, thus requiring fewer signal lines using less area. Decoders electrically connected between the control logic unit and the floating point processor decode the control signals to provide the FPU signals. If the number of control signals is one less than the number of FPU signals, a priority encoder is used as the decoder, unless the FPU signals include a power savings signal. Otherwise a custom decoder is used. The most active signal of the group of FPU signals is selected as the signal to be eliminated when a priority encoder is used.

Reduced area floating point processor control logic utilizing a decoder

A device for distributing a serial stream of commands and associated data to a parallel array of processing units so that the data processed by the parallel processing units can be recombined in the original order in which the serial stream was received. The command distributor of the invention hands out commands to the parallel processing units using a true 'first come, first serve' algorithm using fast bus arbitration hardware. Each parallel processing unit requests data to be input when all of its data has been processed, and bus arbitration is used to prevent conflict when a plurality of requests are received. The ID of the processor to which a command is assigned is used in recombining the processed data into a serial data stream having the same order as the original. Means are also provided by which single commands which require considerable processing may be executed in parallel on more than one of the processors, with each portion of the result coming from a different processor, yet maintaining the sequentiality of the output data stream. Processing speed is further enhanced by broadcasting global commands to all processors at once.

Growing community of inventors

Fort Collins, CO, United States of America

Theodore G Rossin