Marvell International Limited

Qlogic Corporation

Theodore Curt White

William W Dennin, Iii

Angel G Perozo

Dinesh Jayabharathi

Yujun Si

Stanley Ka Fai Cheong

Lim Hudiono

Stanley K Cheong

Aurelio J Cruz

William W Dennin

Thanh H Le

Chau Tran

Joseph G Kriscunas

A disk drive system comprising a disk controller and a buffer memory. The disk controller is configured to receive, from a host, data to be written to a disk, and read, from the disk, data to be transmitted to the host. The buffer memory is configured to store the data read from the disk prior to the data read from the disk being transmitted to the host, and store the data received from the host prior to the data received from the host being written to the disk. The disk controller is further configured to correct errors in the data read from the disk prior to the data read from the disk being stored in the buffer memory.

System and method for in-line error correction for storage systems

A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Method and apparatus for efficiently transferring data in bursts from a storage device to a host

A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

System and method for transferring data in storage controllers

Controller for storage device with improved burst efficiency

A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Power save module for storage controllers

A disk controller comprising a disk formatter configured to receive data being transferred between a disk and a host. A buffer controller is in communication with the disk formatter, a buffer configured to store the data being transferred between the disk and the host, and the host. The buffer is external to each of the disk controller and the host. The buffer controller is configured to regulate transfer of the data between the buffer and the disk formatter. An error correction module is in communication with the disk formatter and the buffer controller. The error correction module is configured to generate an error correction mask to correct errors in the data. The error correction mask is applied to the data prior to the buffer controller transferring the data to the buffer.

A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

System and method for reading and writing data using storage controllers

The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage device, wherein the first memory storage device and the error correction module simultaneously receive data from a storage disk before being buffered for transfer to a host system. The ECC module provides error correction mask before any data is transferred from the first memory storage device to a second memory buffer.

A system includes a data holding module that at least one of stores and receives data based on a first clock signal of a first clock domain. A data output module receives the data from the data holding module and selectively outputs the data based on a load signal and a second clock signal of a second clock domain which is asynchronous to the first clock domain. A synchronization process module generates the load signal based on a state of the data output module.

System and method for configuration register synchronization

A calibration module for a data storage control system. The calibration system includes a programmable delay module configured to i) receive a data strobe signal, ii) receive a delay value, and iii) output a delayed data strobe signal to a buffer based on the delay value, wherein data is read from the buffer based on the delayed data strobe signal. The calibration module further includes a delay calculation module configured to calculate the delay value based on a comparison between the data strobe signal and the delayed data strobe signal.

Method and system for automatic calibration of a DQS signal in a storage controller

A buffer control system for a data storage device controller comprises a command module and a burst module. The command module receives first channel data from a first channel having a first data format and second channel data from a second channel having a second data format and converts the first channel data and the second channel data to respective data packets each having a third data format that is different than the first data format and the second data format. The burst module that selectively transmits the data packets having the third data format to a memory in a single write burst.

System and method for a DDR SDRAM controller

A controller and a method for interfacing with a storage medium. Access to a buffer memory via a multi-channel bus is arbitrated. DWFT (Data Wedge Format Table) entries stored in the buffer memory are read and cached in a DWFT cache memory. Data is transferred to and from the storage medium through a storage medium interface. The storage medium interface accesses the sectors of the storage medium based on their physical locations, as defined by the cached DWFT entries. The multi-channel bus includes a DWFT channel to which DWFT cache circuitry is connected. In a DWFT tenure, the DWFT cache circuitry reads the DWFT entries stored in the buffer memory, and caches the DWFT entries in the DWFT cache memory.

Controller for hard disk drive having DWFT (data wedge format table) cache with high-priority initial cache fill

A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.

Write validation

A calibration system for a data storage device includes a memory and a memory control module. The memory buffers data between a host and the data storage device and generates a data strobe signal. The memory control module selectively adjusts a delay of the data strobe signal. Data is read from the memory based on the data strobe signal.

A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory ('SDRAM'), or Double Data Rate-Synchronous Dynamic Random Access Memory ('DDR') comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.

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Rancho Santa Margarita, CA, United States of America

Theodore Curt White