Unisys Corporation

Theodore C White

Jayesh V Sheth

Kha Nguyen

Dan T Tran

Paul B Ricci

Richard A Cowgill

Craig Weaver Harris

Chung W Wong

Bruce Edward Moolenaar

Javesh Vrajlal Sheth

A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

Dual bus network cache controller system having rapid invalidation

A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.

Dual bus system with multiple processors having data coherency

A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.

Dual bus computer network using dual busses with dual spy modules

A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses to select addresses of words which appear for write operations.

Cache controller utilizing a state machine for controlling invalidations

In accordance with the present invention, a high speed two-part storage interface unit includes--1) a primary I/O port (input/output port) that couples to a plurality of data processing modules; 2) a secondary I/O port that couples to a main memory module, 3) input circuits for receiving three types of write commands and one type of read command from the data processing modules, 4) several write execution modules which are serially-coupled to a time-shared memory, and 5) a control circuit by which the write commands and read commands are performed. In one preferred embodiment, write commands are executed over several clock cycles by passing each such command with its write data word through the write execution modules in a pipelined fashion; read commands are executed at a rate of one command per clock cycle; a read command temporarily preempts the execution of any write command; an interrupt signal on the secondary I/O port stops the execution of read commands and write commands from the primary I/O port and enables data words to be transferred on the secondary I/O port; and write commands can be received on the primary I/O port while data is being transferred on the secondary I/O port.

High speed two-port interface unit where read commands suspend partially

Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait. That signal is removed when that Read-Modify-Write operation is completed.

Information processing system having multiple modules and a memory on a

An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

Interbus interface module

A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

Configurable network using dual system busses with common protocol

An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.

Dual bus communication system connecting multiple processors to multiple

An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.

Timer access control apparatus

A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

Inhibit write apparatus and method for preventing bus lockout

A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

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Tustin, CA, United States of America

Theodore C White