Formation, Inc.

Theodore A Franks

Charles L Kapeghian

An address recall system coupled to a processor to permit operator examination of a predetermined number of executed system addresses. A processor system address is manually inserted to the recall system. When a system address being executed compares with the operator address setting, an address equality signal is generated. The recall system logic generates either a stop or interrupt state for the processor responsive to actuation of another manually operated input switch. Addresses being executed by the processor are stored in a push down memory stack within the recall system. When an address equality signal is generated, one or more of the consecutively executed addresses contained in the memory stack may be manually displayed in the reverse order of execution.

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Cinnaminson, NJ, United States of America

Theodore A Franks